prev_cmp_dptrafficlight.qmsg

用VHDL实现交通灯的功能 很实用的 我认为比其他的的交通灯程序更好

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.528 ns register register " "Info: Estimated most critical path is register to register delay of 8.528 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst14\|count_p\[7\] 1 REG LAB_X45_Y16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X45_Y16; Fanout = 4; REG Node = 'int_div:inst14\|count_p\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst14|count_p[7] } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.114 ns) 1.418 ns int_div:inst14\|LessThan0~974 2 COMB LAB_X45_Y17 1 " "Info: 2: + IC(1.304 ns) + CELL(0.114 ns) = 1.418 ns; Loc. = LAB_X45_Y17; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~974'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.418 ns" { int_div:inst14|count_p[7] int_div:inst14|LessThan0~974 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 2.071 ns int_div:inst14\|LessThan0~975 3 COMB LAB_X45_Y17 2 " "Info: 3: + IC(0.539 ns) + CELL(0.114 ns) = 2.071 ns; Loc. = LAB_X45_Y17; Fanout = 2; COMB Node = 'int_div:inst14\|LessThan0~975'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { int_div:inst14|LessThan0~974 int_div:inst14|LessThan0~975 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 2.724 ns int_div:inst14\|LessThan0~976 4 COMB LAB_X45_Y17 1 " "Info: 4: + IC(0.211 ns) + CELL(0.442 ns) = 2.724 ns; Loc. = LAB_X45_Y17; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~976'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { int_div:inst14|LessThan0~975 int_div:inst14|LessThan0~976 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.442 ns) 4.084 ns int_div:inst14\|LessThan0~978 5 COMB LAB_X44_Y15 1 " "Info: 5: + IC(0.918 ns) + CELL(0.442 ns) = 4.084 ns; Loc. = LAB_X44_Y15; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~978'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { int_div:inst14|LessThan0~976 int_div:inst14|LessThan0~978 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 4.737 ns int_div:inst14\|LessThan0~981 6 COMB LAB_X44_Y15 1 " "Info: 6: + IC(0.361 ns) + CELL(0.292 ns) = 4.737 ns; Loc. = LAB_X44_Y15; Fanout = 1; COMB Node = 'int_div:inst14\|LessThan0~981'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { int_div:inst14|LessThan0~978 int_div:inst14|LessThan0~981 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.590 ns) 5.630 ns int_div:inst14\|LessThan0~979 7 COMB LAB_X45_Y15 2 " "Info: 7: + IC(0.303 ns) + CELL(0.590 ns) = 5.630 ns; Loc. = LAB_X45_Y15; Fanout = 2; COMB Node = 'int_div:inst14\|LessThan0~979'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { int_div:inst14|LessThan0~981 int_div:inst14|LessThan0~979 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.590 ns) 6.283 ns int_div:inst14\|LessThan0~980 8 COMB LAB_X45_Y15 25 " "Info: 8: + IC(0.063 ns) + CELL(0.590 ns) = 6.283 ns; Loc. = LAB_X45_Y15; Fanout = 25; COMB Node = 'int_div:inst14\|LessThan0~980'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { int_div:inst14|LessThan0~979 int_div:inst14|LessThan0~980 } "NODE_NAME" } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.133 ns) + CELL(1.112 ns) 8.528 ns int_div:inst14\|count_p\[6\] 9 REG LAB_X45_Y17 3 " "Info: 9: + IC(1.133 ns) + CELL(1.112 ns) = 8.528 ns; Loc. = LAB_X45_Y17; Fanout = 3; REG Node = 'int_div:inst14\|count_p\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.245 ns" { int_div:inst14|LessThan0~980 int_div:inst14|count_p[6] } "NODE_NAME" } } { "int_div.vhd" "" { Text "F:/DPA_4_TrafficLight/int_div.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.696 ns ( 43.34 % ) " "Info: Total cell delay = 3.696 ns ( 43.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.832 ns ( 56.66 % ) " "Info: Total interconnect delay = 4.832 ns ( 56.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.528 ns" { int_div:inst14|count_p[7] int_div:inst14|LessThan0~974 int_div:inst14|LessThan0~975 int_div:inst14|LessThan0~976 int_div:inst14|LessThan0~978 int_div:inst14|LessThan0~981 int_div:inst14|LessThan0~979 int_div:inst14|LessThan0~980 int_div:inst14|count_p[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X32_Y14 X42_Y27 " "Info: The peak interconnect region extends from location X32_Y14 to location X42_Y27" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}