📄 scanled.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY scanled IS
PORT (
d: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --输入要显示的数据
clk1k: IN STD_LOGIC;
seg: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --数码管段输出引脚
dig: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) --数码管选择输出引脚
);
END ENTITY;
ARCHITECTURE one OF scanled IS
BEGIN
dig <= "01" WHEN clk1k = '0' ELSE "10";
seg <= d(7 DOWNTO 4) WHEN clk1k = '0' else d(3 DOWNTO 0);
END;
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