8.tan.qmsg

实现对ad的控制并用7279芯片进行显示

{ "Info" "ITDB_TH_RESULT" "ADC0809:inst3\|current_state.st3 eoc clk 5.525 ns register " "Info: th for register \"ADC0809:inst3\|current_state.st3\" (data pin = \"eoc\", clock pin = \"clk\") is 5.525 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.467 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.467 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 99 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 99; CLK Node = 'clk'" {  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "" { clk } "NODE_NAME" } "" } } { "8.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/888-8/888-2/8.bdf" { { 240 -88 80 256 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns ADC0809:inst3\|t 2 REG LC_X15_Y13_N4 8 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X15_Y13_N4; Fanout = 8; REG Node = 'ADC0809:inst3\|t'" {  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "1.965 ns" { clk ADC0809:inst3|t } "NODE_NAME" } "" } } { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.322 ns) + CELL(0.711 ns) 8.467 ns ADC0809:inst3\|current_state.st3 3 REG LC_X8_Y13_N4 2 " "Info: 3: + IC(4.322 ns) + CELL(0.711 ns) = 8.467 ns; Loc. = LC_X8_Y13_N4; Fanout = 2; REG Node = 'ADC0809:inst3\|current_state.st3'" {  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "5.033 ns" { ADC0809:inst3|t ADC0809:inst3|current_state.st3 } "NODE_NAME" } "" } } { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 36.79 % ) " "Info: Total cell delay = 3.115 ns ( 36.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.352 ns ( 63.21 % ) " "Info: Total interconnect delay = 5.352 ns ( 63.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "8.467 ns" { clk ADC0809:inst3|t ADC0809:inst3|current_state.st3 } "NODE_NAME" } "" } } { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "8.467 ns" { clk clk~out0 ADC0809:inst3|t ADC0809:inst3|current_state.st3 } { 0.000ns 0.000ns 1.030ns 4.322ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 89 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.957 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.957 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns eoc 1 PIN PIN_28 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 3; PIN Node = 'eoc'" {  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "" { eoc } "NODE_NAME" } "" } } { "8.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/888-8/888-2/8.bdf" { { 256 -88 80 272 "eoc" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.881 ns) + CELL(0.607 ns) 2.957 ns ADC0809:inst3\|current_state.st3 2 REG LC_X8_Y13_N4 2 " "Info: 2: + IC(0.881 ns) + CELL(0.607 ns) = 2.957 ns; Loc. = LC_X8_Y13_N4; Fanout = 2; REG Node = 'ADC0809:inst3\|current_state.st3'" {  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "1.488 ns" { eoc ADC0809:inst3|current_state.st3 } "NODE_NAME" } "" } } { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 70.21 % ) " "Info: Total cell delay = 2.076 ns ( 70.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.881 ns ( 29.79 % ) " "Info: Total interconnect delay = 0.881 ns ( 29.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "2.957 ns" { eoc ADC0809:inst3|current_state.st3 } "NODE_NAME" } "" } } { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "2.957 ns" { eoc eoc~out0 ADC0809:inst3|current_state.st3 } { 0.000ns 0.000ns 0.881ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "8.467 ns" { clk ADC0809:inst3|t ADC0809:inst3|current_state.st3 } "NODE_NAME" } "" } } { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "8.467 ns" { clk clk~out0 ADC0809:inst3|t ADC0809:inst3|current_state.st3 } { 0.000ns 0.000ns 1.030ns 4.322ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "8" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/888-8/888-2/db/8.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/888-8/888-2/" "" "2.957 ns" { eoc ADC0809:inst3|current_state.st3 } "NODE_NAME" } "" } } { "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera.quartus.ii.v5.1.sp2-lz0/quartus51sp2/quartus51sp2/bin/Technology_Viewer.qrui" "2.957 ns" { eoc eoc~out0 ADC0809:inst3|current_state.st3 } { 0.000ns 0.000ns 0.881ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk clk1 ADC0809:inst3\|t1 10.405 ns register " "Info: Minimum tco from clock \"clk\" to destination pin \"clk1\" through registe