8.map.qmsg

实现对ad的控制并用7279芯片进行显示

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 08 12:16:23 2008 " "Info: Processing started: Thu May 08 12:16:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 8 -c 8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 8 -c 8" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hd7279.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hd7279.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hd7279-behav " "Info: Found design unit 1: hd7279-behav" {  } { { "hd7279.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/hd7279.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 hd7279 " "Info: Found entity 1: hd7279" {  } { { "hd7279.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/hd7279.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc0809.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adc0809.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADC0809-behav " "Info: Found design unit 1: ADC0809-behav" {  } { { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADC0809 " "Info: Found entity 1: ADC0809" {  } { { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "8.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 8.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 8 " "Info: Found entity 1: 8" {  } { { "8.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/888-8/888-2/8.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "8 " "Info: Elaborating entity \"8\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hd7279 hd7279:inst " "Info: Elaborating entity \"hd7279\" for hierarchy \"hd7279:inst\"" {  } { { "8.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/888-8/888-2/8.bdf" { { 192 520 704 384 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "chann hd7279.vhd(54) " "Info (10035): Verilog HDL or VHDL information at hd7279.vhd(54): object \"chann\" declared but not used" {  } { { "hd7279.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/hd7279.vhd" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "t hd7279.vhd(67) " "Warning (10492): VHDL Process Statement warning at hd7279.vhd(67): signal \"t\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "hd7279.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/hd7279.vhd" 67 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cp2 hd7279.vhd(67) " "Warning (10492): VHDL Process Statement warning at hd7279.vhd(67): signal \"cp2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "hd7279.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/hd7279.vhd" 67 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RST_N hd7279.vhd(72) " "Warning (10492): VHDL Process Statement warning at hd7279.vhd(72): signal \"RST_N\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "hd7279.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/hd7279.vhd" 72 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "hd7279.vhd(188) " "Info (10425): VHDL Case Statement information at hd7279.vhd(188): OTHERS choice is never selected" {  } { { "hd7279.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/hd7279.vhd" 188 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADC0809 ADC0809:inst3 " "Info: Elaborating entity \"ADC0809\" for hierarchy \"ADC0809:inst3\"" {  } { { "8.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator/桌面/888-8/888-2/8.bdf" { { 184 160 336 408 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "qq adc0809.vhd(26) " "Info (10035): Verilog HDL or VHDL information at adc0809.vhd(26): object \"qq\" declared but not used" {  } { { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 26 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "temp adc0809.vhd(27) " "Info (10035): Verilog HDL or VHDL information at adc0809.vhd(27): object \"temp\" declared but not used" {  } { { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 27 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "count4 adc0809.vhd(32) " "Info (10035): Verilog HDL or VHDL information at adc0809.vhd(32): object \"count4\" declared but not used" {  } { { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 32 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "dp adc0809.vhd(34) " "Info (10035): Verilog HDL or VHDL information at adc0809.vhd(34): object \"dp\" declared but not used" {  } { { "adc0809.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/888-8/888-2/adc0809.vhd" 34 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}