8.map.rpt

实现对ad的控制并用7279芯片进行显示

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; Analysis & Synthesis Equations ;
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The equations can be found in C:/Documents and Settings/Administrator/桌面/888-8/888-2/8.map.eqn.


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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition
    Info: Processing started: Thu May 08 12:16:23 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 8 -c 8
Info: Found 2 design units, including 1 entities, in source file hd7279.vhd
    Info: Found design unit 1: hd7279-behav
    Info: Found entity 1: hd7279
Info: Found 2 design units, including 1 entities, in source file adc0809.vhd
    Info: Found design unit 1: ADC0809-behav
    Info: Found entity 1: ADC0809
Info: Found 1 design units, including 1 entities, in source file 8.bdf
    Info: Found entity 1: 8
Info: Elaborating entity "8" for the top level hierarchy
Info: Elaborating entity "hd7279" for hierarchy "hd7279:inst"
Info (10035): Verilog HDL or VHDL information at hd7279.vhd(54): object "chann" declared but not used
Warning (10492): VHDL Process Statement warning at hd7279.vhd(67): signal "t" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at hd7279.vhd(67): signal "cp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at hd7279.vhd(72): signal "RST_N" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at hd7279.vhd(188): OTHERS choice is never selected
Info: Elaborating entity "ADC0809" for hierarchy "ADC0809:inst3"
Info (10035): Verilog HDL or VHDL information at adc0809.vhd(26): object "qq" declared but not used
Info (10035): Verilog HDL or VHDL information at adc0809.vhd(27): object "temp" declared but not used
Info (10035): Verilog HDL or VHDL information at adc0809.vhd(32): object "count4" declared but not used
Info (10035): Verilog HDL or VHDL information at adc0809.vhd(34): object "dp" declared but not used
Warning (10492): VHDL Process Statement warning at adc0809.vhd(52): signal "d" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc0809.vhd(53): OTHERS choice is never selected
Warning (10631): VHDL Process Statement warning at adc0809.vhd(37): signal or variable "regl" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "regl" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10492): VHDL Process Statement warning at adc0809.vhd(71): signal "t" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(84): signal "t1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(96): signal "regl" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(100): signal "regl" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(101): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(102): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(103): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(104): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(105): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(106): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(107): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc0809.vhd(108): OTHERS choice is never selected
Warning (10492): VHDL Process Statement warning at adc0809.vhd(111): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(112): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(113): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(114): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(115): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(116): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(117): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(118): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(119): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(121): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc0809.vhd(122): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc0809.vhd(123): OTHERS choice is never selected
Warning (10492): VHDL Process Statement warning at adc0809.vhd(126): signal "count1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc0809.vhd(137): OTHERS choice is never selected
Warning (10492): VHDL Process Statement warning at adc0809.vhd(140): signal "count2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc0809.vhd(151): OTHERS choice is never selected
Warning (10492): VHDL Process Statement warning at adc0809.vhd(153): signal "count3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc0809.vhd(160): OTHERS choice is never selected
Warning (10492): VHDL Process Statement warning at adc0809.vhd(162): signal "abc_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc0809.vhd(171): OTHERS choice is never selected
Warning: Reduced register "hd7279:inst|cmd_tmp[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "hd7279:inst|cmd_tmp[5]" with stuck data_in port to stuck value GND
Info: Power-up level of register "hd7279:inst|cmd_tmp[4]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "hd7279:inst|cmd_tmp[4]" with stuck data_in port to stuck value VCC
Warning: Reduced register "hd7279:inst|cmd_tmp[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "hd7279:inst|seg_cnt[2]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "hd7279:inst|cmd_tmp[2]" merged to single register "hd7279:inst|cmd_tmp[7]", power-up level changed
Info: State machine "|8|ADC0809:inst3|current_state" contains 7 states
Info: State machine "|8|hd7279:inst|state" contains 12 states
Info: Selected Auto state machine encoding method for state machine "|8|ADC0809:inst3|current_state"
Info: Encoding result for state machine "|8|ADC0809:inst3|current_state"
    Info: Completed encoding using 7 state bits
        Info: Encoded state bit "ADC0809:inst3|current_state.st6"
        Info: Encoded state bit "ADC0809:inst3|current_state.st5"
        Info: Encoded state bit "ADC0809:inst3|current_state.st4"
        Info: Encoded state bit "ADC0809:inst3|current_state.st3"
        Info: Encoded state bit "ADC0809:inst3|current_state.st2"
        Info: Encoded state bit "ADC0809:inst3|current_state.st1"
        Info: Encoded state bit "ADC0809:inst3|current_state.st0"
    Info: State "|8|ADC0809:inst3|current_state.st0" uses code string "0000000"
    Info: State "|8|ADC0809:inst3|current_state.st1" uses code string "0000011"
    Info: State "|8|ADC0809:inst3|current_state.st2" uses code string "0000101"
    Info: State "|8|ADC0809:inst3|current_state.st3" uses code string "0001001"
    Info: State "|8|ADC0809:inst3|current_state.st4" uses code string "0010001"
    Info: State "|8|ADC0809:inst3|current_state.st5" uses code string "0100001"
    Info: State "|8|ADC0809:inst3|current_state.st6" uses code string "1000001"
Info: Selected Auto state machine encoding method for state machine "|8|hd7279:inst|state"
Info: Encoding result for state machine "|8|hd7279:inst|state"
    Info: Completed encoding using 12 state bits
        Info: Encoded state bit "hd7279:inst|state.finish"
        Info: Encoded state bit "hd7279:inst|state.shift_key_high1"
        Info: Encoded state bit "hd7279:inst|state.shift_key_high"
        Info: Encoded state bit "hd7279:inst|state.shift_key_low"
        Info: Encoded state bit "hd7279:inst|state.shift_data_high"
        Info: Encoded state bit "hd7279:inst|state.shift_data_low"
        Info: Encoded state bit "hd7279:inst|state.next_delay"
        Info: Encoded state bit "hd7279:inst|state.shift_cmd_high"
        Info: Encoded state bit "hd7279:inst|state.shift_cmd_low"
        Info: Encoded state bit "hd7279:inst|state.start_delay"
        Info: Encoded state bit "hd7279:inst|state.start"
        Info: Encoded state bit "hd7279:inst|state.idle"
    Info: State "|8|hd7279:inst|state.idle" uses code string "000000000000"
    Info: State "|8|hd7279:inst|state.start" uses code string "000000000011"
    Info: State "|8|hd7279:inst|state.start_delay" uses code string "000000000101"
    Info: State "|8|hd7279:inst|state.shift_cmd_low" uses code string "000000001001"
    Info: State "|8|hd7279:inst|state.shift_cmd_high" uses code string "000000010001"
    Info: State "|8|hd7279:inst|state.next_delay" uses code string "000000100001"
    Info: State "|8|hd7279:inst|state.shift_data_low" uses code string "000001000001"
    Info: State "|8|hd7279:inst|state.shift_data_high" uses code string "000010000001"
    Info: State "|8|hd7279:inst|state.shift_key_low" uses code string "000100000001"
    Info: State "|8|hd7279:inst|state.shift_key_high" uses code string "001000000001"
    Info: State "|8|hd7279:inst|state.shift_key_high1" uses code string "010000000001"
    Info: State "|8|hd7279:inst|state.finish" uses code string "100000000001"
Info: Registers with preset signals will power-up high
Info: Implemented 480 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 18 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 449 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 36 warnings
    Info: Processing ended: Thu May 08 12:16:32 2008
    Info: Elapsed time: 00:00:10