hd7279.vhd

实现对ad的控制并用7279芯片进行显示

--FPGA控制7279的程序

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;

entity hd7279 is
	port (
		--以下是引脚信号
	
		CLK       :IN      STD_LOGIC;  --系统时钟
		RST_N     :IN      STD_LOGIC;  --系统复位
	--	CLK_S     :IN      STD_LOGIC;  --7279时序的状态机时钟,周期为20us
		--外部控制接口与本模块之间的信号
		--WR_N      :IN      STD_LOGIC;  --外部写信号
		--RD_N      :IN      STD_LOGIC;  --外部读信号
		--KEY_EN    :OUT     STD_LOGIC;  --存在有效键值, 高电平为存在有效键值, 外部接口读走数据后变低
		--ADDR  	  :IN      STD_LOGIC_VECTOR(2 downto 0);  --地址信号
		D_BUS1,D_BUS2,D_BUS3 	  :IN      STD_LOGIC_VECTOR(6 downto 0);  --指令,数据输入及键盘值输出
		--与7279之间的信号
		--KEY7279   :IN      STD_LOGIC;  --7279的键盘信号，有键按下时为低电平，平时为高电平
			key7279: in STD_LOGIC; 
		abc : in STD_LOGIC_VECTOR(2 downto 0);
		D_BUS4 	  :IN      STD_LOGIC_VECTOR(6 downto 0);
			CLK7279,clk2   :OUT     STD_LOGIC;  --7279的时钟信号
		CS7279    :OUT     STD_LOGIC;  --7279的片选信号
	
		DAT7279   :INOUT   STD_LOGIC; --7279数据信号
		channel: out STD_LOGIC_VECTOR(2 downto 0)
		--OUT7279   :OUT     STD_LOGIC_VECTOR(7 downto 0)   --7279键盘键值输出信号,测试时用
		);
end hd7279;

ARCHITECTURE behav OF hd7279 IS
CONSTANT NDC_7279	: std_logic_vector (7 downto 0) := x"90";  --下载数据不译码,
CONSTANT RDKY_7279	: std_logic_vector (7 downto 0) := x"15";  --读键盘数据指令 
   TYPE STATE_TYPE is (IDLE, START, START_DELAY, SHIFT_CMD_LOW, 
					SHIFT_CMD_HIGH,	NEXT_DELAY,  SHIFT_DATA_LOW, SHIFT_DATA_HIGH, 
					SHIFT_KEY_LOW, SHIFT_KEY_HIGH, SHIFT_KEY_HIGH1, FINISH );
signal state : STATE_TYPE;
SIGNAL data_tmp     : STD_LOGIC_VECTOR (7 downto 0); --进入START状态后,操作数据缓存
signal count: integer; 
SIGNAL seg_cnt		: INTEGER RANGE 0 to 7;			 --数码管计数器,从右到左一共8个数码管
SIGNAL cmd_tmp      : STD_LOGIC_VECTOR (7 downto 0); --保存操作命令到移位缓存
SIGNAL delay_cnt	: INTEGER RANGE 0 to 3;
SIGNAL scmd_cnt     : INTEGER RANGE 0 to 7;    
signal cp2:std_logic;
signal t:std_logic;
SIGNAL sdata_cnt    : INTEGER RANGE 0 to 7;
signal dp,dp1		: std_logic; 
signal key_7279_tmp: STD_LOGIC_VECTOR (7 downto 0);
signal key_7279: STD_LOGIC_VECTOR (7 downto 0);
signal chann: STD_LOGIC_VECTOR(2 downto 0);
begin
	dp<='0';dp1<='1';
p1: process(clk)                    ----分频
begin
if (clk'event and clk='1') then
if (count =200) then
count<= 0;
t <= not t;
else
count<= count + 1;
end if;
end if;
cp2<=t;clk2<=cp2;
end process p1;

p2:process(cp2)
begin
  if(RST_N='0')  then
     state <= IDLE;
		
		CS7279 <= '1';
		CLK7279 <= '0';
		DAT7279 <= 'Z';
		state <= IDLE;

	elsif (cp2'event and cp2='1') then
	  	
		case state is
			when IDLE =>
			   if (KEY7279 = '0') then
					cmd_tmp <= RDKY_7279;--为了测试读键盘操作
					DAT7279 <= 'Z';
					 	
					
					state <= START; 
			  else
				  if (seg_cnt = 3) then
						seg_cnt <= 0;
				  else
						seg_cnt <= seg_cnt + 1;						
				  end if;
					cmd_tmp <= NDC_7279(7 downto 3) & CONV_STD_LOGIC_VECTOR(seg_cnt,3);
					if(seg_cnt=0) then
					data_tmp <= dp&D_bus1;
					end if;
					if(seg_cnt=1) then
					data_tmp<=dp&D_BUS2;
					end if;
					if(seg_cnt=2) then
					data_tmp<=dp1&D_BUS3;
					end if;
					if(seg_cnt=3) then
					data_tmp<=dp&D_BUS4;
					end if;
					state <= START; 
				end if;				
			when START =>
				delay_cnt <= 3;
				CS7279 <= '0';			--7279片选置低,开始4次延时,即80us
				CLK7279 <= '0';			--设置时钟为低
				state <= START_DELAY;
			
			--开始发送命令字-------------------------------------------------
			when START_DELAY =>
				if (delay_cnt > 1) then
					delay_cnt <= delay_cnt - 1;
				else
					scmd_cnt <= 7;		--80us延时结束,开始送命令字
					state <= SHIFT_CMD_LOW;
				end if;
			when SHIFT_CMD_LOW =>		--1位数据送到数据线上
				DAT7279 <= cmd_tmp(scmd_cnt);	--用命令字的二级缓存做
				CLK7279 <= '1';			--时钟信号由低变高
				state <= SHIFT_CMD_HIGH;
			when SHIFT_CMD_HIGH =>
				CLK7279 <= '0';		--一外时钟后,时钟信号由高变低
				if (scmd_cnt > 0) then
					scmd_cnt <= scmd_cnt - 1;
					state <= SHIFT_CMD_LOW;					
				--当为双字节操作时,交替间断的延时
				else
					state <= NEXT_DELAY;
					delay_cnt <= 3;
				end if;
			
			--开始发送8位数据------------------------------------------------
			when NEXT_DELAY =>
				if (delay_cnt >1) then
					delay_cnt <= delay_cnt - 1;	--进行读取按键
				
				elsif (cmd_tmp = RDKY_7279) then	--当为键盘接收指令时
					sdata_cnt <= 7;
					state <= SHIFT_KEY_LOW;			--进行读取按键
				else
					sdata_cnt <= 7;
					state <= SHIFT_DATA_LOW;		--80us延时结束,进入数据传输
				end if;
			when SHIFT_DATA_LOW =>					--1位数据送到数据线上
				DAT7279 <= data_tmp(sdata_cnt);
				CLK7279 <= '1';						--时钟信号由低变高
				state <= SHIFT_DATA_HIGH;
			when SHIFT_DATA_HIGH =>
				CLK7279 <= '0';						--时钟信号由高变低
				if (sdata_cnt > 0) then					
					sdata_cnt <= sdata_cnt - 1;
					state <= SHIFT_DATA_LOW;
				else
					state <= FINISH;
				end if;
			--读取按键值-----------------------------------------------------
			when SHIFT_KEY_LOW =>
				CLK7279 <= '1';						--时钟信号由低变高,DAT7279变为输入状态
				DAT7279 <= 'Z';
				state <= SHIFT_KEY_HIGH;
			when SHIFT_KEY_HIGH =>					--保证一个时钟周期的建立时间
				--key_7279(sdata_cnt) <= DAT7279;
				key_7279_tmp(sdata_cnt) <= DAT7279;
				state <= SHIFT_KEY_HIGH1;
			when SHIFT_KEY_HIGH1 =>
				CLK7279 <= '0';						--低电平后为一个时钟周期的保持时间
				if (sdata_cnt > 0) then					
					sdata_cnt <= sdata_cnt - 1;
					state <= SHIFT_KEY_LOW;
				else
					if (KEY7279 = '0') then			--当读取完后,KEY7279仍为0才能确定读取的为有效值
						key_7279 <= key_7279_tmp;
					end if;
					state <= FINISH;
				end if;
			--结束操作-------------------------------------------------------
			when FINISH =>
				CS7279 <= '1';		--7279片选置高,结束操作
				state <= IDLE;				
			when others =>
				NULL;
				
		end case;
	end if;
	
	
end process p2;
--chann<=key_7279 (2 downto 0);
channel<=key_7279(2 downto 0); 
end;