test_bench.v

来自「此程序为用VERLOG HDL编写的一个完整的3位加法器。」· Verilog 代码 · 共 23 行

`timescale 1 ns/1 ns
module test_bench;
    reg  [2:0] r_a,r_b;
    reg        r_ci;
    wire [2:0] w_s;
    wire       w_co;
    parameter  clock=20;
    integer i,j,k;
    adder_3 i0 (.s(w_s), .co(w_co), .a(r_a), .b(r_b), .ci(r_ci));
      initial begin
            for(i=0;i<8;i=i+1)
            for(j=0;j<8;j=j+1)
            for(k=0;k<2;k=k+1)
            begin
             r_a=i;r_b=j;r_ci=k;
            #clock ;
            end
       end
     initial begin //monitor 
       $monitor($time,,"a=%b b=%b ci=%b s=%b co=%b",r_a,r_b,r_ci,w_s,w_co);
 end
 endmodule