adder_3.v

来自「此程序为用VERLOG HDL编写的一个完整的3位加法器。」· Verilog 代码 · 共 11 行

module adder_3(s,co,a,b,ci);
    input  [2:0] a,b;
    input        ci;
    output [2:0] s;
    output       co;
    wire w0,w1,w2;
    adder_1 i0 (.co(w0), .s(s[0]), .a(a[0]), .b(b[0]), .ci(ci));
    adder_1 i1 (.co(w1), .s(s[1]), .a(a[1]), .b(b[1]), .ci(w0));
    adder_1 i2 (.co(co), .s(s[2]), .a(a[2]), .b(b[2]), .ci(w1));
endmodule