test.v

次程序为用VRILOG HDL 编写的交通灯控制程序

`timescale 1s/1s
module test;
reg clk,reset;
wire  agreen,ayellow,ared,bgreen,byellow,bred;
     
parameter cycle=1;

trafficlight light(.agreen(agreen),.ayellow(ayellow),.ared(ared),.bgreen(bgreen),.byellow(byellow),.bred(bred),.clk(clk),.reset(reset));
initial
    begin
        clk=0;
        reset=1;
        #cycle reset=0;
    end
always #cycle clk=~clk;
endmodule