trafficlight.v

来自「次程序为用VRILOG HDL 编写的交通灯控制程序」· Verilog 代码 · 共 58 行

`timescale 1s/1s
module trafficlight(agreen,ayellow,ared,bgreen,byellow,bred,clk,reset);
    input clk,reset;
    output agreen,ared,ayellow,bgreen,bred,byellow;
      reg[1:0]  state,next_state;
    integer count;
    reg mclk;
    reg k;
    reg agreen,ared,ayellow,bgreen,bred,byellow;
    
    parameter s0=0;
    parameter s1=1;
    parameter s2=2;
    parameter s3=3;
  
    
    always @(posedge mclk or posedge reset)
    begin
     if(reset)   state<=s0; 
     else if(mclk) state<=next_state;

      case(state)
        s0:    begin   {agreen,ayellow,ared,bgreen,byellow,bred}=6'b100001;
                        k=1; next_state<=s1;
                end
        s1:     begin  {agreen,ayellow,ared,bgreen,byellow,bred}=6'b010001;
                        k=0;state<=s2;
                end
        s2:     begin  {agreen,ayellow,ared,bgreen,byellow,bred}=6'b001100;
                        k=1;state<=s3;
                end
        s3:     begin  {agreen,ayellow,ared,bgreen,byellow,bred}=6'b001010;
                       k=0;state<=s0;
                end
        default:state<=s0;
    endcase
end
    
    always@(posedge clk)
    begin
      if(k==0) begin 
         if(count!=0) begin count=count-1; mclk<=0;        
                    end
         else   begin 
                            count=20;
                            mclk<=1;end
              end 
      else   begin 
           if(count!=0)      
                    begin count=count-1; mclk<=0;        
                      end
           else   begin 
                 count=2;
                 mclk<=1; end   
           end 
end
endmodule