sample.map.eqn

运行在FPGA上的Verilog程序

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--current_state.state1 is current_state.state1
--operation mode is normal

current_state.state1_lut_out = !current_state.state0;
current_state.state1 = DFFEAS(current_state.state1_lut_out, clk, !reset, , enable, , , , );


--current_state.state4 is current_state.state4
--operation mode is normal

current_state.state4_lut_out = current_state.state3;
current_state.state4 = DFFEAS(current_state.state4_lut_out, clk, !reset, , enable, , , , );


--current_state.state3 is current_state.state3
--operation mode is normal

current_state.state3_lut_out = current_state.state2 & EOC;
current_state.state3 = DFFEAS(current_state.state3_lut_out, clk, !reset, , enable, , , , );


--A1L5 is OE~0
--operation mode is normal

A1L5 = current_state.state4 # current_state.state3;


--current_state.state0 is current_state.state0
--operation mode is normal

current_state.state0_lut_out = !current_state.state4;
current_state.state0 = DFFEAS(current_state.state0_lut_out, clk, !reset, , enable, , , , );


--current_state.state2 is current_state.state2
--operation mode is normal

current_state.state2_lut_out = current_state.state1 # current_state.state2 & (!EOC);
current_state.state2 = DFFEAS(current_state.state2_lut_out, clk, !reset, , enable, , , , );


--dataOut[0]$latch is dataOut[0]$latch
--operation mode is normal

dataOut[0]$latch = current_state.state4 & dataIn[0] # !current_state.state4 & (dataOut[0]$latch);


--dataOut[1]$latch is dataOut[1]$latch
--operation mode is normal

dataOut[1]$latch = current_state.state4 & dataIn[1] # !current_state.state4 & (dataOut[1]$latch);


--dataOut[2]$latch is dataOut[2]$latch
--operation mode is normal

dataOut[2]$latch = current_state.state4 & dataIn[2] # !current_state.state4 & (dataOut[2]$latch);


--dataOut[3]$latch is dataOut[3]$latch
--operation mode is normal

dataOut[3]$latch = current_state.state4 & dataIn[3] # !current_state.state4 & (dataOut[3]$latch);


--dataOut[4]$latch is dataOut[4]$latch
--operation mode is normal

dataOut[4]$latch = current_state.state4 & dataIn[4] # !current_state.state4 & (dataOut[4]$latch);


--dataOut[5]$latch is dataOut[5]$latch
--operation mode is normal

dataOut[5]$latch = current_state.state4 & dataIn[5] # !current_state.state4 & (dataOut[5]$latch);


--dataOut[6]$latch is dataOut[6]$latch
--operation mode is normal

dataOut[6]$latch = current_state.state4 & dataIn[6] # !current_state.state4 & (dataOut[6]$latch);


--dataOut[7]$latch is dataOut[7]$latch
--operation mode is normal

dataOut[7]$latch = current_state.state4 & dataIn[7] # !current_state.state4 & (dataOut[7]$latch);


--clk is clk
--operation mode is input

clk = INPUT();


--reset is reset
--operation mode is input

reset = INPUT();


--enable is enable
--operation mode is input

enable = INPUT();


--EOC is EOC
--operation mode is input

EOC = INPUT();


--dataIn[0] is dataIn[0]
--operation mode is input

dataIn[0] = INPUT();


--dataIn[1] is dataIn[1]
--operation mode is input

dataIn[1] = INPUT();


--dataIn[2] is dataIn[2]
--operation mode is input

dataIn[2] = INPUT();


--dataIn[3] is dataIn[3]
--operation mode is input

dataIn[3] = INPUT();


--dataIn[4] is dataIn[4]
--operation mode is input

dataIn[4] = INPUT();


--dataIn[5] is dataIn[5]
--operation mode is input

dataIn[5] = INPUT();


--dataIn[6] is dataIn[6]
--operation mode is input

dataIn[6] = INPUT();


--dataIn[7] is dataIn[7]
--operation mode is input

dataIn[7] = INPUT();


--ALE is ALE
--operation mode is output

ALE = OUTPUT(current_state.state1);


--START is START
--operation mode is output

START = OUTPUT(current_state.state1);


--OE is OE
--operation mode is output

OE = OUTPUT(A1L5);


--ADDA is ADDA
--operation mode is output

ADDA = OUTPUT(VCC);


--dataOut[0] is dataOut[0]
--operation mode is output

dataOut[0] = OUTPUT(dataOut[0]$latch);


--dataOut[1] is dataOut[1]
--operation mode is output

dataOut[1] = OUTPUT(dataOut[1]$latch);


--dataOut[2] is dataOut[2]
--operation mode is output

dataOut[2] = OUTPUT(dataOut[2]$latch);


--dataOut[3] is dataOut[3]
--operation mode is output

dataOut[3] = OUTPUT(dataOut[3]$latch);


--dataOut[4] is dataOut[4]
--operation mode is output

dataOut[4] = OUTPUT(dataOut[4]$latch);


--dataOut[5] is dataOut[5]
--operation mode is output

dataOut[5] = OUTPUT(dataOut[5]$latch);


--dataOut[6] is dataOut[6]
--operation mode is output

dataOut[6] = OUTPUT(dataOut[6]$latch);


--dataOut[7] is dataOut[7]
--operation mode is output

dataOut[7] = OUTPUT(dataOut[7]$latch);


--dataINT is dataINT
--operation mode is output

dataINT = OUTPUT(current_state.state4);