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📄 sample.fit.eqn

📁 运行在FPGA上的Verilog程序
💻 EQN
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--current_state.state1 is current_state.state1 at LC_X8_Y6_N5
--operation mode is normal

current_state.state1_lut_out = !current_state.state0;
current_state.state1 = DFFEAS(current_state.state1_lut_out, GLOBAL(clk), !GLOBAL(reset), , enable, , , , );


--current_state.state3 is current_state.state3 at LC_X8_Y6_N4
--operation mode is normal

current_state.state3_lut_out = EOC & current_state.state2;
current_state.state3 = DFFEAS(current_state.state3_lut_out, GLOBAL(clk), !GLOBAL(reset), , enable, , , , );


--A1L5 is OE~0 at LC_X8_Y6_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

current_state.state4_qfbk = current_state.state4;
A1L5 = current_state.state3 # current_state.state4_qfbk;

--current_state.state4 is current_state.state4 at LC_X8_Y6_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

current_state.state4 = DFFEAS(A1L5, GLOBAL(clk), !GLOBAL(reset), , enable, current_state.state3, , , VCC);


--current_state.state0 is current_state.state0 at LC_X8_Y6_N6
--operation mode is normal

current_state.state0_lut_out = !current_state.state4;
current_state.state0 = DFFEAS(current_state.state0_lut_out, GLOBAL(clk), !GLOBAL(reset), , enable, , , , );


--current_state.state2 is current_state.state2 at LC_X8_Y6_N8
--operation mode is normal

current_state.state2_lut_out = current_state.state1 # !EOC & current_state.state2;
current_state.state2 = DFFEAS(current_state.state2_lut_out, GLOBAL(clk), !GLOBAL(reset), , enable, , , , );


--dataOut[0]$latch is dataOut[0]$latch at LC_X17_Y6_N2
--operation mode is normal

dataOut[0]$latch = GLOBAL(current_state.state4) & dataIn[0] # !GLOBAL(current_state.state4) & (dataOut[0]$latch);


--dataOut[1]$latch is dataOut[1]$latch at LC_X8_Y4_N2
--operation mode is normal

dataOut[1]$latch = GLOBAL(current_state.state4) & dataIn[1] # !GLOBAL(current_state.state4) & (dataOut[1]$latch);


--dataOut[2]$latch is dataOut[2]$latch at LC_X16_Y11_N2
--operation mode is normal

dataOut[2]$latch = GLOBAL(current_state.state4) & dataIn[2] # !GLOBAL(current_state.state4) & (dataOut[2]$latch);


--dataOut[3]$latch is dataOut[3]$latch at LC_X6_Y9_N2
--operation mode is normal

dataOut[3]$latch = GLOBAL(current_state.state4) & dataIn[3] # !GLOBAL(current_state.state4) & (dataOut[3]$latch);


--dataOut[4]$latch is dataOut[4]$latch at LC_X8_Y7_N3
--operation mode is normal

dataOut[4]$latch = GLOBAL(current_state.state4) & (dataIn[4]) # !GLOBAL(current_state.state4) & dataOut[4]$latch;


--dataOut[5]$latch is dataOut[5]$latch at LC_X11_Y10_N2
--operation mode is normal

dataOut[5]$latch = GLOBAL(current_state.state4) & dataIn[5] # !GLOBAL(current_state.state4) & (dataOut[5]$latch);


--dataOut[6]$latch is dataOut[6]$latch at LC_X10_Y6_N2
--operation mode is normal

dataOut[6]$latch = GLOBAL(current_state.state4) & dataIn[6] # !GLOBAL(current_state.state4) & (dataOut[6]$latch);


--dataOut[7]$latch is dataOut[7]$latch at LC_X18_Y11_N3
--operation mode is normal

dataOut[7]$latch = GLOBAL(current_state.state4) & (dataIn[7]) # !GLOBAL(current_state.state4) & dataOut[7]$latch;


--clk is clk at PIN_93
--operation mode is input

clk = INPUT();


--reset is reset at PIN_144
--operation mode is input

reset = INPUT();


--enable is enable at PIN_143
--operation mode is input

enable = INPUT();


--EOC is EOC at PIN_11
--operation mode is input

EOC = INPUT();


--dataIn[0] is dataIn[0] at PIN_39
--operation mode is input

dataIn[0] = INPUT();


--dataIn[1] is dataIn[1] at PIN_40
--operation mode is input

dataIn[1] = INPUT();


--dataIn[2] is dataIn[2] at PIN_41
--operation mode is input

dataIn[2] = INPUT();


--dataIn[3] is dataIn[3] at PIN_42
--operation mode is input

dataIn[3] = INPUT();


--dataIn[4] is dataIn[4] at PIN_47
--operation mode is input

dataIn[4] = INPUT();


--dataIn[5] is dataIn[5] at PIN_48
--operation mode is input

dataIn[5] = INPUT();


--dataIn[6] is dataIn[6] at PIN_49
--operation mode is input

dataIn[6] = INPUT();


--dataIn[7] is dataIn[7] at PIN_50
--operation mode is input

dataIn[7] = INPUT();


--ALE is ALE at PIN_74
--operation mode is output

ALE = OUTPUT(current_state.state1);


--START is START at PIN_75
--operation mode is output

START = OUTPUT(current_state.state1);


--OE is OE at PIN_76
--operation mode is output

OE = OUTPUT(A1L5);


--ADDA is ADDA at PIN_73
--operation mode is output

ADDA = OUTPUT(VCC);


--dataOut[0] is dataOut[0] at PIN_122
--operation mode is output

dataOut[0] = OUTPUT(dataOut[0]$latch);


--dataOut[1] is dataOut[1] at PIN_121
--operation mode is output

dataOut[1] = OUTPUT(dataOut[1]$latch);


--dataOut[2] is dataOut[2] at PIN_120
--operation mode is output

dataOut[2] = OUTPUT(dataOut[2]$latch);


--dataOut[3] is dataOut[3] at PIN_119
--operation mode is output

dataOut[3] = OUTPUT(dataOut[3]$latch);


--dataOut[4] is dataOut[4] at PIN_114
--operation mode is output

dataOut[4] = OUTPUT(dataOut[4]$latch);


--dataOut[5] is dataOut[5] at PIN_113
--operation mode is output

dataOut[5] = OUTPUT(dataOut[5]$latch);


--dataOut[6] is dataOut[6] at PIN_112
--operation mode is output

dataOut[6] = OUTPUT(dataOut[6]$latch);


--dataOut[7] is dataOut[7] at PIN_111
--operation mode is output

dataOut[7] = OUTPUT(dataOut[7]$latch);


--dataINT is dataINT at PIN_110
--operation mode is output

dataINT = OUTPUT(current_state.state4);




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