watchgai.tan.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 29 " "Warning: Circuit may not operate. Detected 29 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "watchgai:inst6\|fen\[4\] watchgai:inst6\|p4\[6\] clk 3.514 ns " "Info: Found hold time violation between source  pin or register \"watchgai:inst6\|fen\[4\]\" and destination pin or register \"watchgai:inst6\|p4\[6\]\" for clock \"clk\" (Hold time is 3.514 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.343 ns + Largest " "Info: + Largest clock skew is 6.343 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.151 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 13.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { clk } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 110 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 110; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.970 ns) 3.404 ns watchgai:inst6\|clk_temp 3 REG LCFF_X23_Y15_N11 2 " "Info: 3: + IC(1.077 ns) + CELL(0.970 ns) = 3.404 ns; Loc. = LCFF_X23_Y15_N11; Fanout = 2; REG Node = 'watchgai:inst6\|clk_temp'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "2.047 ns" { clk~clkctrl watchgai:inst6|clk_temp } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.669 ns) + CELL(0.000 ns) 5.073 ns watchgai:inst6\|clk_temp~clkctrl 4 COMB CLKCTRL_G8 18 " "Info: 4: + IC(1.669 ns) + CELL(0.000 ns) = 5.073 ns; Loc. = CLKCTRL_G8; Fanout = 18; COMB Node = 'watchgai:inst6\|clk_temp~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.669 ns" { watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(0.970 ns) 7.112 ns watchgai:inst6\|fen\[4\] 5 REG LCFF_X30_Y15_N17 27 " "Info: 5: + IC(1.069 ns) + CELL(0.970 ns) = 7.112 ns; Loc. = LCFF_X30_Y15_N17; Fanout = 27; REG Node = 'watchgai:inst6\|fen\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "2.039 ns" { watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.206 ns) 8.081 ns watchgai:inst6\|Mux~4004 6 COMB LCCOMB_X31_Y15_N6 1 " "Info: 6: + IC(0.763 ns) + CELL(0.206 ns) = 8.081 ns; Loc. = LCCOMB_X31_Y15_N6; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~4004'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.969 ns" { watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.647 ns) 9.695 ns watchgai:inst6\|Mux~4005 7 COMB LCCOMB_X29_Y15_N20 1 " "Info: 7: + IC(0.967 ns) + CELL(0.647 ns) = 9.695 ns; Loc. = LCCOMB_X29_Y15_N20; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~4005'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.614 ns" { watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.678 ns) + CELL(0.000 ns) 11.373 ns watchgai:inst6\|Mux~4005clkctrl 8 COMB CLKCTRL_G15 6 " "Info: 8: + IC(1.678 ns) + CELL(0.000 ns) = 11.373 ns; Loc. = CLKCTRL_G15; Fanout = 6; COMB Node = 'watchgai:inst6\|Mux~4005clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.678 ns" { watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.206 ns) 13.151 ns watchgai:inst6\|p4\[6\] 9 REG LCCOMB_X30_Y14_N16 1 " "Info: 9: + IC(1.572 ns) + CELL(0.206 ns) = 13.151 ns; Loc. = LCCOMB_X30_Y14_N16; Fanout = 1; REG Node = 'watchgai:inst6\|p4\[6\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.778 ns" { watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[6] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.099 ns ( 31.17 % ) " "Info: Total cell delay = 4.099 ns ( 31.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.052 ns ( 68.83 % ) " "Info: Total interconnect delay = 9.052 ns ( 68.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "13.151 ns" { clk clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[6] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "13.151 ns" { clk clk~combout clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[6] } { 0.000ns 0.000ns 0.257ns 1.077ns 1.669ns 1.069ns 0.763ns 0.967ns 1.678ns 1.572ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.206ns 0.647ns 0.000ns 0.206ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.808 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 6.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { clk } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 110 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 110; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.970 ns) 3.404 ns watchgai:inst6\|clk_temp 3 REG LCFF_X23_Y15_N11 2 " "Info: 3: + IC(1.077 ns) + CELL(0.970 ns) = 3.404 ns; Loc. = LCFF_X23_Y15_N11; Fanout = 2; REG Node = 'watchgai:inst6\|clk_temp'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "2.047 ns" { clk~clkctrl watchgai:inst6|clk_temp } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.669 ns) + CELL(0.000 ns) 5.073 ns watchgai:inst6\|clk_temp~clkctrl 4 COMB CLKCTRL_G8 18 " "Info: 4: + IC(1.669 ns) + CELL(0.000 ns) = 5.073 ns; Loc. = CLKCTRL_G8; Fanout = 18; COMB Node = 'watchgai:inst6\|clk_temp~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.669 ns" { watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(0.666 ns) 6.808 ns watchgai:inst6\|fen\[4\] 5 REG LCFF_X30_Y15_N17 27 " "Info: 5: + IC(1.069 ns) + CELL(0.666 ns) = 6.808 ns; Loc. = LCFF_X30_Y15_N17; Fanout = 27; REG Node = 'watchgai:inst6\|fen\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.735 ns" { watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 40.19 % ) " "Info: Total cell delay = 2.736 ns ( 40.19 % )"