watchgai.tan.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register watchgai:inst6\|p4\[5\] register watchgai:inst6\|bwm\[5\] 91.58 MHz 10.92 ns Internal " "Info: Clock \"clk\" has Internal fmax of 91.58 MHz between source register \"watchgai:inst6\|p4\[5\]\" and destination register \"watchgai:inst6\|bwm\[5\]\" (period= 10.92 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.816 ns + Longest register register " "Info: + Longest register to register delay is 4.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns watchgai:inst6\|p4\[5\] 1 REG LCCOMB_X29_Y15_N16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X29_Y15_N16; Fanout = 1; REG Node = 'watchgai:inst6\|p4\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { watchgai:inst6|p4[5] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.919 ns) + CELL(0.651 ns) 2.570 ns watchgai:inst6\|Mux~3947 2 COMB LCCOMB_X30_Y16_N12 1 " "Info: 2: + IC(1.919 ns) + CELL(0.651 ns) = 2.570 ns; Loc. = LCCOMB_X30_Y16_N12; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~3947'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "2.570 ns" { watchgai:inst6|p4[5] watchgai:inst6|Mux~3947 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.206 ns) 3.146 ns watchgai:inst6\|Mux~3948 3 COMB LCCOMB_X30_Y16_N0 1 " "Info: 3: + IC(0.370 ns) + CELL(0.206 ns) = 3.146 ns; Loc. = LCCOMB_X30_Y16_N0; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~3948'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.576 ns" { watchgai:inst6|Mux~3947 watchgai:inst6|Mux~3948 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 3.714 ns watchgai:inst6\|Mux~3949 4 COMB LCCOMB_X30_Y16_N22 1 " "Info: 4: + IC(0.362 ns) + CELL(0.206 ns) = 3.714 ns; Loc. = LCCOMB_X30_Y16_N22; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~3949'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.568 ns" { watchgai:inst6|Mux~3948 watchgai:inst6|Mux~3949 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 4.708 ns watchgai:inst6\|Mux~3951 5 COMB LCCOMB_X30_Y16_N16 1 " "Info: 5: + IC(0.370 ns) + CELL(0.624 ns) = 4.708 ns; Loc. = LCCOMB_X30_Y16_N16; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~3951'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.994 ns" { watchgai:inst6|Mux~3949 watchgai:inst6|Mux~3951 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.816 ns watchgai:inst6\|bwm\[5\] 6 REG LCFF_X30_Y16_N17 1 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 4.816 ns; Loc. = LCFF_X30_Y16_N17; Fanout = 1; REG Node = 'watchgai:inst6\|bwm\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.108 ns" { watchgai:inst6|Mux~3951 watchgai:inst6|bwm[5] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 870 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.795 ns ( 37.27 % ) " "Info: Total cell delay = 1.795 ns ( 37.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.021 ns ( 62.73 % ) " "Info: Total interconnect delay = 3.021 ns ( 62.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "4.816 ns" { watchgai:inst6|p4[5] watchgai:inst6|Mux~3947 watchgai:inst6|Mux~3948 watchgai:inst6|Mux~3949 watchgai:inst6|Mux~3951 watchgai:inst6|bwm[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "4.816 ns" { watchgai:inst6|p4[5] watchgai:inst6|Mux~3947 watchgai:inst6|Mux~3948 watchgai:inst6|Mux~3949 watchgai:inst6|Mux~3951 watchgai:inst6|bwm[5] } { 0.000ns 1.919ns 0.370ns 0.362ns 0.370ns 0.000ns } { 0.000ns 0.651ns 0.206ns 0.206ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.144 ns - Smallest " "Info: - Smallest clock skew is -6.144 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.032 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { clk } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 110 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 110; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.970 ns) 3.407 ns watchgai:inst6\|clk_temp1 3 REG LCFF_X45_Y10_N19 2 " "Info: 3: + IC(1.080 ns) + CELL(0.970 ns) = 3.407 ns; Loc. = LCFF_X45_Y10_N19; Fanout = 2; REG Node = 'watchgai:inst6\|clk_temp1'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "2.050 ns" { clk~clkctrl watchgai:inst6|clk_temp1 } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.896 ns) + CELL(0.000 ns) 5.303 ns watchgai:inst6\|clk_temp1~clkctrl 4 COMB CLKCTRL_G6 20 " "Info: 4: + IC(1.896 ns) + CELL(0.000 ns) = 5.303 ns; Loc. = CLKCTRL_G6; Fanout = 20; COMB Node = 'watchgai:inst6\|clk_temp1~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.896 ns" { watchgai:inst6|clk_temp1 watchgai:inst6|clk_temp1~clkctrl } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.063 ns) + CELL(0.666 ns) 7.032 ns watchgai:inst6\|bwm\[5\] 5 REG LCFF_X30_Y16_N17 1 " "Info: 5: + IC(1.063 ns) + CELL(0.666 ns) = 7.032 ns; Loc. = LCFF_X30_Y16_N17; Fanout = 1; REG Node = 'watchgai:inst6\|bwm\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.729 ns" { watchgai:inst6|clk_temp1~clkctrl watchgai:inst6|bwm[5] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 870 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 38.91 % ) " "Info: Total cell delay = 2.736 ns ( 38.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.296 ns ( 61.09 % ) " "Info: Total interconnect delay = 4.296 ns ( 61.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "7.032 ns" { clk clk~clkctrl watchgai:inst6|clk_temp1 watchgai:inst6|clk_temp1~clkctrl watchgai:inst6|bwm[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.032 ns" { clk clk~combout clk~clkctrl watchgai:inst6|clk_temp1 watchgai:inst6|clk_temp1~clkctrl watchgai:inst6|bwm[5] } { 0.000ns 0.000ns 0.257ns 1.080ns 1.896ns 1.063ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.176 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { clk } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.357 ns clk~clkctrl 2 COMB CLKCTRL_G2 110 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G2; Fanout = 110; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.970 ns) 3.404 ns watchgai:inst6\|clk_temp 3 REG LCFF_X23_Y15_N11 2 " "Info: 3: + IC(1.077 ns) + CELL(0.970 ns) = 3.404 ns; Loc. = LCFF_X23_Y15_N11; Fanout = 2; REG Node = 'watchgai:inst6\|clk_temp'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "2.047 ns" { clk~clkctrl watchgai:inst6|clk_temp } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.669 ns) + CELL(0.000 ns) 5.073 ns watchgai:inst6\|clk_temp~clkctrl 4 COMB CLKCTRL_G8 18 " "Info: 4: + IC(1.669 ns) + CELL(0.000 ns) = 5.073 ns; Loc. = CLKCTRL_G8; Fanout = 18; COMB Node = 'watchgai:inst6\|clk_temp~clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.669 ns" { watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(0.970 ns) 7.112 ns watchgai:inst6\|fen\[4\] 5 REG LCFF_X30_Y15_N17 27 " "Info: 5: + IC(1.069 ns) + CELL(0.970 ns) = 7.112 ns; Loc. = LCFF_X30_Y15_N17; Fanout = 27; REG Node = 'watchgai:inst6\|fen\[4\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "2.039 ns" { watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.206 ns) 8.081 ns watchgai:inst6\|Mux~4004 6 COMB LCCOMB_X31_Y15_N6 1 " "Info: 6: + IC(0.763 ns) + CELL(0.206 ns) = 8.081 ns; Loc. = LCCOMB_X31_Y15_N6; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~4004'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.969 ns" { watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.647 ns) 9.695 ns watchgai:inst6\|Mux~4005 7 COMB LCCOMB_X29_Y15_N20 1 " "Info: 7: + IC(0.967 ns) + CELL(0.647 ns) = 9.695 ns; Loc. = LCCOMB_X29_Y15_N20; Fanout = 1; COMB Node = 'watchgai:inst6\|Mux~4005'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.614 ns" { watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.678 ns) + CELL(0.000 ns) 11.373 ns watchgai:inst6\|Mux~4005clkctrl 8 COMB CLKCTRL_G15 6 " "Info: 8: + IC(1.678 ns) + CELL(0.000 ns) = 11.373 ns; Loc. = CLKCTRL_G15; Fanout = 6; COMB Node = 'watchgai:inst6\|Mux~4005clkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.678 ns" { watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.206 ns) 13.176 ns watchgai:inst6\|p4\[5\] 9 REG LCCOMB_X29_Y15_N16 1 " "Info: 9: + IC(1.597 ns) + CELL(0.206 ns) = 13.176 ns; Loc. = LCCOMB_X29_Y15_N16; Fanout = 1; REG Node = 'watchgai:inst6\|p4\[5\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.803 ns" { watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[5] } "NODE_NAME" } "" } } { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.099 ns ( 31.11 % ) " "Info: Total cell delay = 4.099 ns ( 31.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.077 ns ( 68.89 % ) " "Info: Total interconnect delay = 9.077 ns ( 68.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "13.176 ns" { clk clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "13.176 ns" { clk clk~combout clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[5] } { 0.000ns 0.000ns 0.257ns 1.077ns 1.669ns 1.069ns 0.763ns 0.967ns 1.678ns 1.597ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.206ns 0.647ns 0.000ns 0.206ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "7.032 ns" { clk clk~clkctrl watchgai:inst6|clk_temp1 watchgai:inst6|clk_temp1~clkctrl watchgai:inst6|bwm[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.032 ns" { clk clk~combout clk~clkctrl watchgai:inst6|clk_temp1 watchgai:inst6|clk_temp1~clkctrl watchgai:inst6|bwm[5] } { 0.000ns 0.000ns 0.257ns 1.080ns 1.896ns 1.063ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "13.176 ns" { clk clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "13.176 ns" { clk clk~combout clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[5] } { 0.000ns 0.000ns 0.257ns 1.077ns 1.669ns 1.069ns 0.763ns 0.967ns 1.678ns 1.597ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.206ns 0.647ns 0.000ns 0.206ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 870 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "4.816 ns" { watchgai:inst6|p4[5] watchgai:inst6|Mux~3947 watchgai:inst6|Mux~3948 watchgai:inst6|Mux~3949 watchgai:inst6|Mux~3951 watchgai:inst6|bwm[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "4.816 ns" { watchgai:inst6|p4[5] watchgai:inst6|Mux~3947 watchgai:inst6|Mux~3948 watchgai:inst6|Mux~3949 watchgai:inst6|Mux~3951 watchgai:inst6|bwm[5] } { 0.000ns 1.919ns 0.370ns 0.362ns 0.370ns 0.000ns } { 0.000ns 0.651ns 0.206ns 0.206ns 0.624ns 0.108ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "7.032 ns" { clk clk~clkctrl watchgai:inst6|clk_temp1 watchgai:inst6|clk_temp1~clkctrl watchgai:inst6|bwm[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.032 ns" { clk clk~combout clk~clkctrl watchgai:inst6|clk_temp1 watchgai:inst6|clk_temp1~clkctrl watchgai:inst6|bwm[5] } { 0.000ns 0.000ns 0.257ns 1.080ns 1.896ns 1.063ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "13.176 ns" { clk clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[5] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "13.176 ns" { clk clk~combout clk~clkctrl watchgai:inst6|clk_temp watchgai:inst6|clk_temp~clkctrl watchgai:inst6|fen[4] watchgai:inst6|Mux~4004 watchgai:inst6|Mux~4005 watchgai:inst6|Mux~4005clkctrl watchgai:inst6|p4[5] } { 0.000ns 0.000ns 0.257ns 1.077ns 1.669ns 1.069ns 0.763ns 0.967ns 1.678ns 1.597ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.206ns 0.647ns 0.000ns 0.206ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_signaltap:auto_signaltap_0\|bypass_reg_out register sld_hub:sld_hub_inst\|hub_tdo 96.14 MHz 10.402 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 96.14 MHz between source register \"sld_signaltap:auto_signaltap_0\|bypass_reg_out\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 10.402 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.944 ns + Longest register register " "Info: + Longest register to register delay is 4.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|bypass_reg_out 1 REG LCFF_X34_Y11_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y11_N11; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|bypass_reg_out'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.647 ns) 1.825 ns sld_hub:sld_hub_inst\|hub_tdo~650 2 COMB LCCOMB_X34_Y13_N24 1 " "Info: 2: + IC(1.178 ns) + CELL(0.647 ns) = 1.825 ns; Loc. = LCCOMB_X34_Y13_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~650'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.825 ns" { sld_signaltap:auto_signaltap_0|bypass_reg_out sld_hub:sld_hub_inst|hub_tdo~650 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.651 ns) 2.860 ns sld_hub:sld_hub_inst\|hub_tdo~653 3 COMB LCCOMB_X34_Y13_N26 1 " "Info: 3: + IC(0.384 ns) + CELL(0.651 ns) = 2.860 ns; Loc. = LCCOMB_X34_Y13_N26; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~653'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.035 ns" { sld_hub:sld_hub_inst|hub_tdo~650 sld_hub:sld_hub_inst|hub_tdo~653 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.624 ns) 3.852 ns sld_hub:sld_hub_inst\|hub_tdo~655 4 COMB LCCOMB_X34_Y13_N2 1 " "Info: 4: + IC(0.368 ns) + CELL(0.624 ns) = 3.852 ns; Loc. = LCCOMB_X34_Y13_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~655'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.992 ns" { sld_hub:sld_hub_inst|hub_tdo~653 sld_hub:sld_hub_inst|hub_tdo~655 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.616 ns) 4.836 ns sld_hub:sld_hub_inst\|hub_tdo~656 5 COMB LCCOMB_X34_Y13_N28 1 " "Info: 5: + IC(0.368 ns) + CELL(0.616 ns) = 4.836 ns; Loc. = LCCOMB_X34_Y13_N28; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~656'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.984 ns" { sld_hub:sld_hub_inst|hub_tdo~655 sld_hub:sld_hub_inst|hub_tdo~656 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.944 ns sld_hub:sld_hub_inst\|hub_tdo 6 REG LCFF_X34_Y13_N29 2 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 4.944 ns; Loc. = LCFF_X34_Y13_N29; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo~656 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.646 ns ( 53.52 % ) " "Info: Total cell delay = 2.646 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.298 ns ( 46.48 % ) " "Info: Total interconnect delay = 2.298 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "4.944 ns" { sld_signaltap:auto_signaltap_0|bypass_reg_out sld_hub:sld_hub_inst|hub_tdo~650 sld_hub:sld_hub_inst|hub_tdo~653 sld_hub:sld_hub_inst|hub_tdo~655 sld_hub:sld_hub_inst|hub_tdo~656 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "4.944 ns" { sld_signaltap:auto_signaltap_0|bypass_reg_out sld_hub:sld_hub_inst|hub_tdo~650 sld_hub:sld_hub_inst|hub_tdo~653 sld_hub:sld_hub_inst|hub_tdo~655 sld_hub:sld_hub_inst|hub_tdo~656 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.178ns 0.384ns 0.368ns 0.368ns 0.000ns } { 0.000ns 0.647ns 0.651ns 0.624ns 0.616ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.007 ns - Smallest " "Info: - Smallest clock skew is 0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.574 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.824 ns) + CELL(0.000 ns) 3.824 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 136 " "Info: 2: + IC(3.824 ns) + CELL(0.000 ns) = 3.824 ns; Loc. = CLKCTRL_G0; Fanout = 136; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.666 ns) 5.574 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X34_Y13_N29 2 " "Info: 3: + IC(1.084 ns) + CELL(0.666 ns) = 5.574 ns; Loc. = LCFF_X34_Y13_N29; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.750 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 11.95 % ) " "Info: Total cell delay = 0.666 ns ( 11.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.908 ns ( 88.05 % ) " "Info: Total interconnect delay = 4.908 ns ( 88.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "5.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.824ns 1.084ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.567 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.824 ns) + CELL(0.000 ns) 3.824 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 136 " "Info: 2: + IC(3.824 ns) + CELL(0.000 ns) = 3.824 ns; Loc. = CLKCTRL_G0; Fanout = 136; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.666 ns) 5.567 ns sld_signaltap:auto_signaltap_0\|bypass_reg_out 3 REG LCFF_X34_Y11_N11 2 " "Info: 3: + IC(1.077 ns) + CELL(0.666 ns) = 5.567 ns; Loc. = LCFF_X34_Y11_N11; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|bypass_reg_out'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.743 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 11.96 % ) " "Info: Total cell delay = 0.666 ns ( 11.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.901 ns ( 88.04 % ) " "Info: Total interconnect delay = 4.901 ns ( 88.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "5.567 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.567 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|bypass_reg_out } { 0.000ns 3.824ns 1.077ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "5.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.824ns 1.084ns } { 0.000ns 0.000ns 0.666ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "5.567 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.567 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|bypass_reg_out } { 0.000ns 3.824ns 1.077ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "4.944 ns" { sld_signaltap:auto_signaltap_0|bypass_reg_out sld_hub:sld_hub_inst|hub_tdo~650 sld_hub:sld_hub_inst|hub_tdo~653 sld_hub:sld_hub_inst|hub_tdo~655 sld_hub:sld_hub_inst|hub_tdo~656 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "4.944 ns" { sld_signaltap:auto_signaltap_0|bypass_reg_out sld_hub:sld_hub_inst|hub_tdo~650 sld_hub:sld_hub_inst|hub_tdo~653 sld_hub:sld_hub_inst|hub_tdo~655 sld_hub:sld_hub_inst|hub_tdo~656 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.178ns 0.384ns 0.368ns 0.368ns 0.000ns } { 0.000ns 0.647ns 0.651ns 0.624ns 0.616ns 0.108ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "5.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.574 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.824ns 1.084ns } { 0.000ns 0.000ns 0.666ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "5.567 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.567 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|bypass_reg_out } { 0.000ns 3.824ns 1.077ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}