watchgai.tan.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "watchgai:inst6\|Mux~4004 " "Info: Detected gated clock \"watchgai:inst6\|Mux~4004\" as buffer" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|Mux~4004" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "watchgai:inst6\|Mux~4005 " "Info: Detected gated clock \"watchgai:inst6\|Mux~4005\" as buffer" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|Mux~4005" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|fen\[2\] " "Info: Detected ripple clock \"watchgai:inst6\|fen\[2\]\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|fen\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|fen\[4\] " "Info: Detected ripple clock \"watchgai:inst6\|fen\[4\]\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|fen\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|fen\[0\] " "Info: Detected ripple clock \"watchgai:inst6\|fen\[0\]\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|fen\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|fen\[1\] " "Info: Detected ripple clock \"watchgai:inst6\|fen\[1\]\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|fen\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|fen\[5\] " "Info: Detected ripple clock \"watchgai:inst6\|fen\[5\]\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|fen\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|fen\[3\] " "Info: Detected ripple clock \"watchgai:inst6\|fen\[3\]\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|fen\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|clk_temp " "Info: Detected ripple clock \"watchgai:inst6\|clk_temp\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|clk_temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "watchgai:inst6\|clk_temp1 " "Info: Detected ripple clock \"watchgai:inst6\|clk_temp1\" as buffer" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 37 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|clk_temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}