watchgai.tan.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off watchgai -c watchgai --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off watchgai -c watchgai --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "watchgai:inst6\|p4\[6\] " "Warning: Node \"watchgai:inst6\|p4\[6\]\" is a latch" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "watchgai:inst6\|p4\[5\] " "Warning: Node \"watchgai:inst6\|p4\[5\]\" is a latch" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "watchgai:inst6\|p4\[4\] " "Warning: Node \"watchgai:inst6\|p4\[4\]\" is a latch" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "watchgai:inst6\|p4\[3\] " "Warning: Node \"watchgai:inst6\|p4\[3\]\" is a latch" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "watchgai:inst6\|p4\[2\] " "Warning: Node \"watchgai:inst6\|p4\[2\]\" is a latch" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "watchgai:inst6\|p4\[1\] " "Warning: Node \"watchgai:inst6\|p4\[1\]\" is a latch" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}