watchgai.fit.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 42 行 · 第 1/5 页

{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.335 ns register register " "Info: Estimated most critical path is register to register delay of 4.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] 1 REG LAB_X33_Y13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X33_Y13; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.624 ns) 1.532 ns sld_hub:sld_hub_inst\|hub_tdo~651 2 COMB LAB_X35_Y13 1 " "Info: 2: + IC(0.908 ns) + CELL(0.624 ns) = 1.532 ns; Loc. = LAB_X35_Y13; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~651'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.532 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~651 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.748 ns) + CELL(0.370 ns) 2.650 ns sld_hub:sld_hub_inst\|hub_tdo~653 3 COMB LAB_X34_Y13 1 " "Info: 3: + IC(0.748 ns) + CELL(0.370 ns) = 2.650 ns; Loc. = LAB_X34_Y13; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~653'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "1.118 ns" { sld_hub:sld_hub_inst|hub_tdo~651 sld_hub:sld_hub_inst|hub_tdo~653 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 3.461 ns sld_hub:sld_hub_inst\|hub_tdo~655 4 COMB LAB_X34_Y13 1 " "Info: 4: + IC(0.187 ns) + CELL(0.624 ns) = 3.461 ns; Loc. = LAB_X34_Y13; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~655'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.811 ns" { sld_hub:sld_hub_inst|hub_tdo~653 sld_hub:sld_hub_inst|hub_tdo~655 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.606 ns) 4.227 ns sld_hub:sld_hub_inst\|hub_tdo~656 5 COMB LAB_X34_Y13 1 " "Info: 5: + IC(0.160 ns) + CELL(0.606 ns) = 4.227 ns; Loc. = LAB_X34_Y13; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~656'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.766 ns" { sld_hub:sld_hub_inst|hub_tdo~655 sld_hub:sld_hub_inst|hub_tdo~656 } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.335 ns sld_hub:sld_hub_inst\|hub_tdo 6 REG LAB_X34_Y13 2 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 4.335 ns; Loc. = LAB_X34_Y13; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo~656 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.332 ns ( 53.79 % ) " "Info: Total cell delay = 2.332 ns ( 53.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.003 ns ( 46.21 % ) " "Info: Total interconnect delay = 2.003 ns ( 46.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "4.335 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~651 sld_hub:sld_hub_inst|hub_tdo~653 sld_hub:sld_hub_inst|hub_tdo~655 sld_hub:sld_hub_inst|hub_tdo~656 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}