watchgai.fit.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 42 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "watchgai:inst6\|clk_temp1  " "Info: Automatically promoted node watchgai:inst6\|clk_temp1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "watchgai:inst6\|clk_temp1~5 " "Info: Destination node watchgai:inst6\|clk_temp1~5" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 37 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|clk_temp1~5" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { watchgai:inst6|clk_temp1~5 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { watchgai:inst6|clk_temp1~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 37 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|clk_temp1" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { watchgai:inst6|clk_temp1 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { watchgai:inst6|clk_temp1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "watchgai:inst6\|clk_temp  " "Info: Automatically promoted node watchgai:inst6\|clk_temp " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "watchgai:inst6\|clk_temp~5 " "Info: Destination node watchgai:inst6\|clk_temp~5" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|clk_temp~5" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { watchgai:inst6|clk_temp~5 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { watchgai:inst6|clk_temp~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 36 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|clk_temp" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { watchgai:inst6|clk_temp } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { watchgai:inst6|clk_temp } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "watchgai:inst6\|Mux~4005  " "Info: Automatically promoted node watchgai:inst6\|Mux~4005 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "watchgai:inst6\|Mux~4005" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { watchgai:inst6|Mux~4005 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { watchgai:inst6|Mux~4005 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|reset_all  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLRN_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLRN_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Destination node sld_signaltap:auto_signaltap_0\|reset_all" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLRN_SIGNAL" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1129 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1129 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~113 " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~113" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1128 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~113" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~113 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~113 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|post_trigger_count_enable~105 " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|post_trigger_count_enable~105" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1017 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|post_trigger_count_enable~105" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable~105 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable~105 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[2\] " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[2\]" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1154 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[2\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[2] } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[2] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|IRSR_D\[2\]~464 " "Info: Destination node sld_hub:sld_hub_inst\|IRSR_D\[2\]~464" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 343 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|IRSR_D\[2\]~464" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_hub:sld_hub_inst|IRSR_D[2]~464 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_hub:sld_hub_inst|IRSR_D[2]~464 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|edq~89 " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|edq~89" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1056 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|edq~89" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|edq~89 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|edq~89 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena~192 " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena~192" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena~192" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~192 } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~192 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "watchgai" "UNKNOWN" "V1" "E:/project/FPGA/project1/watchgai/db/watchgai.quartus_db" { Floorplan "E:/project/FPGA/project1/watchgai/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } "" } } { "E:/project/FPGA/project1/watchgai/watchgai.fld" "" { Floorplan "E:/project/FPGA/project1/watchgai/watchgai.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}