watchgai.map.rpt

利用FPGA的V4开发板制作的电子表

; sld_advanced_trigger_9      ; NONE          ; String                            ;
; sld_advanced_trigger_10     ; NONE          ; String                            ;
+-----------------------------+---------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ;
+--------------------------+----------------------------------+---------+
; Parameter Name           ; Value                            ; Type    ;
+--------------------------+----------------------------------+---------+
; sld_hub_ip_version       ; 1                                ; Untyped ;
; sld_hub_ip_minor_version ; 3                                ; Untyped ;
; sld_common_ip_version    ; 0                                ; Untyped ;
; device_family            ; Cyclone II                       ; Untyped ;
; n_nodes                  ; 1                                ; Untyped ;
; n_sel_bits               ; 1                                ; Untyped ;
; n_node_ir_bits           ; 7                                ; Untyped ;
; node_info                ; 00011000000000000110111000000000 ; Binary  ;
; compilation_mode         ; 0                                ; Untyped ;
+--------------------------+----------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                             ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; 0              ; auto_signaltap_0 ; 2                   ; 2                ; 128          ; 1              ; 0                       ; no              ; no               ; 0                          ; 0                       ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/project/FPGA/project1/watchgai/watchgai.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Wed May 07 15:57:48 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off watchgai -c watchgai
Info: Found 2 design units, including 1 entities, in source file watchgai.vhd
    Info: Found design unit 1: watchgai-jishu
    Info: Found entity 1: watchgai
Info: Found 1 design units, including 1 entities, in source file biaogai.bdf
    Info: Found entity 1: biaogai
Info: Elaborating entity "biaogai" for the top level hierarchy
Info: Elaborating entity "watchgai" for hierarchy "watchgai:inst6"
Warning (10541): VHDL Signal Declaration warning at watchgai.vhd(38): used implicit default value for signal "beef" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Info (10035): Verilog HDL or VHDL information at watchgai.vhd(51): object "ma" declared but not used
Info (10035): Verilog HDL or VHDL information at watchgai.vhd(51): object "fa" declared but not used
Info (10035): Verilog HDL or VHDL information at watchgai.vhd(51): object "sa" declared but not used
Warning (10492): VHDL Process Statement warning at watchgai.vhd(79): signal "clk_temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at watchgai.vhd(127): signal "miao" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at watchgai.vhd(435): signal "fen" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at watchgai.vhd(741): signal "shi" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at watchgai.vhd(77): signal or variable "p4" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "p4" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 3 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd
    Info: Found design unit 1: sld_signaltap_pack
    Info: Found design unit 2: sld_signaltap-rtl
    Info: Found entity 1: sld_signaltap
Info: Found 14 design units, including 7 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd
    Info: Found design unit 1: sld_ela_control-rtl
    Info: Found design unit 2: sld_ela_level_seq_mgr-rtl
    Info: Found design unit 3: sld_ela_state_machine-rtl
    Info: Found design unit 4: sld_ela_seg_state_machine-rtl
    Info: Found design unit 5: sld_ela_post_trigger_counter-rtl
    Info: Found design unit 6: sld_ela_segment_mgr-rtl
    Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl
    Info: Found entity 1: sld_ela_control
    Info: Found entity 2: sld_ela_level_seq_mgr
    Info: Found entity 3: sld_ela_state_machine
    Info: Found entity 4: sld_ela_seg_state_machine
    Info: Found entity 5: sld_ela_post_trigger_counter
    Info: Found entity 6: sld_ela_segment_mgr
    Info: Found entity 7: sld_ela_basic_multi_level_trigger
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 4 design units, including 2 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd
    Info: Found design unit 1: sld_mbpmg-rtl
    Info: Found design unit 2: sld_sbpmg-rtl
    Info: Found entity 1: sld_mbpmg
    Info: Found entity 2: sld_sbpmg
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_7jc.tdf
    Info: Found entity 1: cntr_7jc
Info: Found 1 design units, including 1 entities, in source file db/cntr_6sb.tdf
    Info: Found entity 1: cntr_6sb
Info