📄 watchgai.map.rpt
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; watchgai.vhd ; yes ; User VHDL File ; E:/project/FPGA/project1/watchgai/watchgai.vhd ;
; biaogai.bdf ; yes ; User Block Diagram/Schematic File ; E:/project/FPGA/project1/watchgai/biaogai.bdf ;
; sld_signaltap.vhd ; yes ; Encrypted Megafunction ; e:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd ;
; sld_ela_control.vhd ; yes ; Encrypted Megafunction ; e:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; e:/altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf ;
; lpm_constant.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/lpm_constant.inc ;
; dffeea.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/dffeea.inc ;
; aglobal51.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/aglobal51.inc ;
; sld_mbpmg.vhd ; yes ; Encrypted Megafunction ; e:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd ;
; lpm_counter.tdf ; yes ; Megafunction ; e:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf ;
; lpm_decode.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/lpm_counter.inc ;
; alt_synch_counter.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/alt_counter_stratix.inc ;
; db/cntr_7jc.tdf ; yes ; Auto-Generated Megafunction ; E:/project/FPGA/project1/watchgai/db/cntr_7jc.tdf ;
; db/cntr_6sb.tdf ; yes ; Auto-Generated Megafunction ; E:/project/FPGA/project1/watchgai/db/cntr_6sb.tdf ;
; lpm_compare.tdf ; yes ; Megafunction ; e:/altera/quartus51/libraries/megafunctions/lpm_compare.tdf ;
; comptree.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/comptree.inc ;
; altshift.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/altshift.inc ;
; db/cmpr_nth.tdf ; yes ; Auto-Generated Megafunction ; E:/project/FPGA/project1/watchgai/db/cmpr_nth.tdf ;
; sld_acquisition_buffer.vhd ; yes ; Encrypted Megafunction ; e:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd ;
; db/cntr_smd.tdf ; yes ; Auto-Generated Megafunction ; E:/project/FPGA/project1/watchgai/db/cntr_smd.tdf ;
; lpm_ff.tdf ; yes ; Megafunction ; e:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf ;
; altsyncram.tdf ; yes ; Megafunction ; e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/lpm_mux.inc ;
; altsyncram.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/altsyncram.inc ;
; a_rdenreg.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_hlb2.tdf ; yes ; Auto-Generated Megafunction ; E:/project/FPGA/project1/watchgai/db/altsyncram_hlb2.tdf ;
; db/cntr_igb.tdf ; yes ; Auto-Generated Megafunction ; E:/project/FPGA/project1/watchgai/db/cntr_igb.tdf ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; e:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; e:/altera/quartus51/libraries/megafunctions/sld_hub.vhd ;
; lpm_decode.tdf ; yes ; Megafunction ; e:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf ;
; declut.inc ; yes ; Other ; e:/altera/quartus51/libraries/megafunctions/declut.inc ;
; db/decode_rpe.tdf ; yes ; Auto-Generated Megafunction ; E:/project/FPGA/project1/watchgai/db/decode_rpe.tdf ;
; sld_dffex.vhd ; yes ; Encrypted Megafunction ; e:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------------+
; Total combinational functions ; 475 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 240 ;
; -- 3 input functions ; 73 ;
; -- <=2 input functions ; 162 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 382 ;
; -- arithmetic mode ; 93 ;
; Total registers ; 266 ;
; I/O pins ; 21 ;
; Total memory bits ; 256 ;
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