watchgai.tan.rpt

利用FPGA的V4开发板制作的电子表

programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                          ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                      ; From                                          ; To                                                                                      ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 1.919 ns                         ; altera_internal_jtag~TMSUTAP                  ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated|dffe1a[1] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 14.676 ns                        ; watchgai:inst6|bwm[7]                         ; data[7]                                                                                 ; clk                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 3.016 ns                         ; altera_internal_jtag~TDO                      ; altera_reserved_tdo                                                                     ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 1.396 ns                         ; altera_internal_jtag                          ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]                              ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A                                      ; None          ; 91.58 MHz ( period = 10.920 ns ) ; watchgai:inst6|p4[5]                          ; watchgai:inst6|bwm[5]                                                                   ; clk                          ; clk                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 96.14 MHz ( period = 10.402 ns ) ; sld_signaltap:auto_signaltap_0|bypass_reg_out ; sld_hub:sld_hub_inst|hub_tdo                                                            ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Hold: 'clk'                           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; watchgai:inst6|fen[4]                         ; watchgai:inst6|p4[6]                                                                    ; clk                          ; clk                          ; 29           ;
; Total number of failed paths                ;                                          ;               ;                                  ;                                               ;                                                                                         ;                              ;                              ; 29           ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20F484C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;