📄 multi.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\mydds\verilog\multi.rpt
multi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\verilog\multi.rpt
multi
** EQUATIONS **
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
-- Node name is 'data_out0'
-- Equation name is 'data_out0', type is output
data_out0 = _LC8_A14;
-- Node name is 'data_out1'
-- Equation name is 'data_out1', type is output
data_out1 = _LC2_A14;
-- Node name is 'data_out2'
-- Equation name is 'data_out2', type is output
data_out2 = _LC7_A14;
-- Node name is 'data_out3'
-- Equation name is 'data_out3', type is output
data_out3 = _LC4_A21;
-- Node name is 'data_out4'
-- Equation name is 'data_out4', type is output
data_out4 = _LC1_A21;
-- Node name is 'data_out5'
-- Equation name is 'data_out5', type is output
data_out5 = _LC3_A21;
-- Node name is 'data_out6'
-- Equation name is 'data_out6', type is output
data_out6 = GND;
-- Node name is 'data_out7'
-- Equation name is 'data_out7', type is output
data_out7 = GND;
-- Node name is '|one_bit_adder:U_0_0|:7'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ001);
_EQ001 = A2 & B1 & !B2
# !A1 & A2 & B1
# A1 & !A2 & B2
# A1 & !B1 & B2;
-- Node name is '|one_bit_adder:U_0_0|:12'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ002);
_EQ002 = A1 & A2 & B1 & B2;
-- Node name is '|one_bit_adder:U_0_1|~8~1'
-- Equation name is '_LC3_A14', type is buried
-- synthesized logic cell
_LC3_A14 = LCELL( _EQ003);
_EQ003 = A2 & !B1 & B2
# !A1 & A2 & B2;
-- Node name is '|one_bit_adder:U_0_1|:8'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = LCELL( _EQ004);
_EQ004 = A3 & B1 & !_LC3_A14
# !A3 & _LC3_A14
# !B1 & _LC3_A14;
-- Node name is '|one_bit_adder:U_0_1|:12'
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = LCELL( _EQ005);
_EQ005 = A2 & A3 & B1 & B2;
-- Node name is '|one_bit_adder:U_0_2|:8'
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = LCELL( _EQ006);
_EQ006 = !A3 & _LC2_A21
# !A3 & _LC5_A21
# !B2 & _LC5_A21
# A3 & B2 & !_LC5_A21;
-- Node name is '|one_bit_adder:U_0_2|:14'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = LCELL( _EQ007);
_EQ007 = A2 & A3 & B1 & B2;
-- Node name is '|one_bit_adder:U_1_0|:7'
-- Equation name is '_LC7_A14', type is buried
_LC7_A14 = LCELL( _EQ008);
_EQ008 = !B3 & _LC4_A14
# !A1 & _LC4_A14
# A1 & B3 & !_LC4_A14;
-- Node name is '|one_bit_adder:U_1_0|:12'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ009);
_EQ009 = A1 & B3 & _LC4_A14;
-- Node name is '|one_bit_adder:U_1_1|:8'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ010);
_EQ010 = A2 & B3 & _LC1_A14 & _LC6_A21
# !B3 & !_LC1_A14 & _LC6_A21
# !A2 & !_LC1_A14 & _LC6_A21
# !B3 & _LC1_A14 & !_LC6_A21
# !A2 & _LC1_A14 & !_LC6_A21
# A2 & B3 & !_LC1_A14 & !_LC6_A21;
-- Node name is '|one_bit_adder:U_1_1|:15'
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = LCELL( _EQ011);
_EQ011 = !A2 & _LC1_A14 & _LC6_A21
# A2 & _LC1_A14 & !_LC6_A21
# A2 & B3 & _LC6_A21;
-- Node name is '|one_bit_adder:U_1_2|:8'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ012);
_EQ012 = A3 & B3 & _LC7_A21 & _LC8_A21
# !A3 & _LC7_A21 & !_LC8_A21
# !B3 & _LC7_A21 & !_LC8_A21
# !A3 & !_LC7_A21 & _LC8_A21
# !B3 & !_LC7_A21 & _LC8_A21
# A3 & B3 & !_LC7_A21 & !_LC8_A21;
-- Node name is '|one_bit_adder:U_1_2|:15'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ013);
_EQ013 = A3 & B3 & _LC7_A21
# !A3 & _LC7_A21 & _LC8_A21
# !B3 & _LC7_A21 & _LC8_A21
# A3 & B3 & _LC8_A21;
-- Node name is ':257'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = LCELL( _EQ014);
_EQ014 = A1 & B1;
Project Information e:\mydds\verilog\multi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,099K
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