📄 add.rpt
字号:
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 4/ 48( 8%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
C: 10/ 96( 10%) 0/ 48( 0%) 3/ 48( 6%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\verilog\add.rpt
add
** EQUATIONS **
op10 : INPUT;
op11 : INPUT;
op12 : INPUT;
op13 : INPUT;
op14 : INPUT;
op15 : INPUT;
op16 : INPUT;
op17 : INPUT;
op20 : INPUT;
op21 : INPUT;
op22 : INPUT;
op23 : INPUT;
op24 : INPUT;
op25 : INPUT;
op26 : INPUT;
op27 : INPUT;
-- Node name is 'result0'
-- Equation name is 'result0', type is output
result0 = _LC1_B14;
-- Node name is 'result1'
-- Equation name is 'result1', type is output
result1 = _LC2_B14;
-- Node name is 'result2'
-- Equation name is 'result2', type is output
result2 = _LC6_B14;
-- Node name is 'result3'
-- Equation name is 'result3', type is output
result3 = _LC5_B14;
-- Node name is 'result4'
-- Equation name is 'result4', type is output
result4 = _LC7_C23;
-- Node name is 'result5'
-- Equation name is 'result5', type is output
result5 = _LC4_C23;
-- Node name is 'result6'
-- Equation name is 'result6', type is output
result6 = _LC3_C23;
-- Node name is 'result7'
-- Equation name is 'result7', type is output
result7 = _LC5_C23;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ001);
_EQ001 = op11 & op21
# op10 & op11 & op20
# op10 & op20 & op21;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ002);
_EQ002 = _LC4_B14 & op12
# _LC4_B14 & op22
# op12 & op22;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ003);
_EQ003 = _LC3_B14 & op23
# _LC3_B14 & op13
# op13 & op23;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ004);
_EQ004 = _LC1_C23 & op24
# _LC1_C23 & op14
# op14 & op24;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C23', type is buried
_LC6_C23 = LCELL( _EQ005);
_EQ005 = _LC2_C23 & op25
# _LC2_C23 & op15
# op15 & op25;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C23', type is buried
_LC8_C23 = LCELL( _EQ006);
_EQ006 = _LC6_C23 & op26
# _LC6_C23 & op16
# op16 & op26;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:147' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ007);
_EQ007 = op10 & !op20
# !op10 & op20;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:156' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = LCELL( _EQ008);
_EQ008 = op10 & op11 & op20 & op21
# !op10 & op11 & !op21
# op11 & !op20 & !op21
# !op10 & !op11 & op21
# !op11 & !op20 & op21
# op10 & !op11 & op20 & !op21;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:157' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ009);
_EQ009 = _LC4_B14 & op12 & op22
# _LC4_B14 & !op12 & !op22
# !_LC4_B14 & op12 & !op22
# !_LC4_B14 & !op12 & op22;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:158' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ010);
_EQ010 = _LC3_B14 & op13 & op23
# _LC3_B14 & !op13 & !op23
# !_LC3_B14 & !op13 & op23
# !_LC3_B14 & op13 & !op23;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:159' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = LCELL( _EQ011);
_EQ011 = _LC1_C23 & op14 & op24
# _LC1_C23 & !op14 & !op24
# !_LC1_C23 & !op14 & op24
# !_LC1_C23 & op14 & !op24;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:160' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = LCELL( _EQ012);
_EQ012 = _LC2_C23 & op15 & op25
# _LC2_C23 & !op15 & !op25
# !_LC2_C23 & !op15 & op25
# !_LC2_C23 & op15 & !op25;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:161' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = LCELL( _EQ013);
_EQ013 = _LC6_C23 & op16 & op26
# _LC6_C23 & !op16 & !op26
# !_LC6_C23 & !op16 & op26
# !_LC6_C23 & op16 & !op26;
-- Node name is '|LPM_ADD_SUB:25|addcore:adder|:162' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ014);
_EQ014 = _LC8_C23 & op17 & op27
# _LC8_C23 & !op17 & !op27
# !_LC8_C23 & !op17 & op27
# !_LC8_C23 & op17 & !op27;
Project Information e:\mydds\verilog\add.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,538K
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