add.vhd

来自「在采用 320x240 屏的设计实验箱上运行」· VHDL 代码 · 共 16 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY add IS
	PORT (op1, op2		: in std_logic_vector(7 downto 0);
		  result       : out std_logic_vector(7 downto 0));
END add;

ARCHITECTURE mm OF add IS
BEGIN
	result <= op1+op2;
    END mm;