zhuan.vhd

在采用 320x240 屏的设计实验箱上运行

            library IEEE;
            use IEEE.std_logic_1164.all;
            use ieee.std_logic_unsigned.all;

            entity zhuan is
            port (
            A: in STD_LOGIC_vector(7 downto 0);
            B: in STD_LOGIC_vector(7 downto 0);
            aout: out STD_LOGIC_vector(3 downto 0);
            bout: out STD_LOGIC_vector(3 downto 0)
            );
            end zhuan;

            architecture mimi of zhuan is
            begin

            aout<=A(7 downto 4);
            bout<=B(7 downto 4);
            end mimi;