📄 mytest.rpt
字号:
|chengfa2:72|one_bit_adder:U_5_0|
|chengfa2:72|one_bit_adder:U_5_1|
|chengfa2:72|one_bit_adder:U_5_2|
|chengfa2:72|one_bit_adder:U_5_3|
|chengfa2:72|one_bit_adder:U_5_4|
|chengfa2:72|one_bit_adder:U_5_5|
|chengfa2:72|one_bit_adder:U_5_6|
|chengfa2:72|one_bit_adder:U_5_7|
|chengfa2:72|one_bit_adder:U_6_0|
|chengfa2:72|one_bit_adder:U_6_1|
|chengfa2:72|one_bit_adder:U_6_2|
|chengfa2:72|one_bit_adder:U_6_3|
|chengfa2:72|one_bit_adder:U_6_4|
|chengfa2:72|one_bit_adder:U_6_5|
|chengfa2:72|one_bit_adder:U_6_6|
|chengfa2:72|one_bit_adder:U_6_7|
|huan:75|
|huan:75|lpm_add_sub:139|
|huan:75|lpm_add_sub:139|addcore:adder|
|huan:75|lpm_add_sub:139|altshift:result_ext_latency_ffs|
|huan:75|lpm_add_sub:139|altshift:carry_ext_latency_ffs|
|huan:75|lpm_add_sub:139|altshift:oflow_ext_latency_ffs|
|huan:75|lpm_add_sub:210|
|huan:75|lpm_add_sub:210|addcore:adder|
|huan:75|lpm_add_sub:210|altshift:result_ext_latency_ffs|
|huan:75|lpm_add_sub:210|altshift:carry_ext_latency_ffs|
|huan:75|lpm_add_sub:210|altshift:oflow_ext_latency_ffs|
|modsel:80|
Device-Specific Information: e:\esd-5_example\dds-320-modu\verilog\mytest.rpt
mytest
***** Logic for device 'mytest' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R O
E E N
S S M V M G M G M M M M F
E E d C d N d N d d d d _ ^
K K K R R a C a D a D a a a a # D n
e e e V P V t I t I t I t t t t T O C
y y y E C E a N a D N M a N a a a a C N E
1 2 3 D S D 7 T 6 C T h 5 T 4 3 2 1 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | Mdata0
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
Key0 | 16 70 | da0832wr
int0 | 17 69 | da_cs
RESERVED | 18 68 | GNDINT
clk | 19 67 | col0
VCCINT | 20 66 | col1
RESERVED | 21 65 | col2
RESERVED | 22 EPF10K10LC84-3 64 | col3
RESERVED | 23 63 | VCCINT
RESERVED | 24 62 | row0
RESERVED | 25 61 | row1
GNDINT | 26 60 | row2
RESERVED | 27 59 | row3
RESERVED | 28 58 | da_out0
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | da_out1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G G G G V G R d d d d d d
C n E E E E E C N N N N C N E a a a a a a
C C S S S S S C D D D D C D S _ _ _ _ _ _
I O E E E E E I I I I I I I E o o o o o o
N N R R R R R N N N N N N N R u u u u u u
T F V V V V V T T T T T T T V t t t t t t
I E E E E E E 7 6 5 4 3 2
G D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\esd-5_example\dds-320-modu\verilog\mytest.rpt
mytest
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
A2 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
A3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
A4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
A5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A6 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
A7 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
A8 6/ 8( 75%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
A9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
A11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
A12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
A13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
A15 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
A16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 7/22( 31%)
A17 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
A18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
A19 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
A20 4/ 8( 50%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 6/22( 27%)
A21 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 10/22( 45%)
A22 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A23 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 1/22( 4%)
B2 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 2/2 0/2 3/22( 13%)
B3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
B4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
B11 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C1 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
C2 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
C3 7/ 8( 87%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
C4 5/ 8( 62%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 4/22( 18%)
C14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 7/22( 31%)
C19 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 6/22( 27%)
C20 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 7/22( 31%)
C22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
C24 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 7/8 ( 87%) 1/8 ( 12%) 7/8 ( 87%) 0/2 2/2 8/22( 36%)
B25 8/8 (100%) 8/8 (100%) 1/8 ( 12%) 0/2 2/2 8/22( 36%)
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 33/53 ( 62%)
Total logic cells used: 244/576 ( 42%)
Total embedded cells used: 15/24 ( 62%)
Total EABs used: 2/3 ( 66%)
Average fan-in: 3.48/4 ( 87%)
Total fan-in: 850/2304 ( 36%)
Total input pins required: 16
Total input I/O cell registers required: 0
Total output pins required: 19
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 244
Total flipflops required: 76
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 40/ 576 ( 6%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 7 8 8 8 8 8 6 8 8 8 8 7 8 8 3 8 8 8 2 4 7 1 4 0 154/7
B: 0 8 8 1 8 0 0 0 0 0 5 0 8 0 0 0 0 0 0 0 0 0 0 0 0 30/8
C: 8 8 7 5 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 4 6 0 8 0 6 60/0
Total: 16 23 23 14 16 8 8 6 8 8 13 8 15 8 16 3 8 8 8 6 10 7 9 4 6 244/15
Device-Specific Information: e:\esd-5_example\dds-320-modu\verilog\mytest.rpt
mytest
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- INPUT 0 0 0 26 clk
2 - - - -- INPUT 0 0 0 18 DC
73 - - A -- INPUT 0 0 0 3 Mdata0
78 - - - 24 INPUT 0 0 0 3 Mdata1
79 - - - 24 INPUT 0 0 0 2 Mdata2
80 - - - 23 INPUT 0 0 0 2 Mdata3
81 - - - 22 INPUT 0 0 0 2 Mdata4
83 - - - 13 INPUT 0 0 0 2 Mdata5
3 - - - 12 INPUT 0 0 0 2 Mdata6
5 - - - 05 INPUT 0 0 0 2 Mdata7
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