📄 modsel.rpt
字号:
- 7 - A 10 AND2 3 0 1 0 :46
- 6 - A 10 OR2 4 0 1 0 :67
- 5 - A 10 OR2 4 0 1 0 :68
- 4 - A 10 OR2 4 0 1 0 :69
- 8 - A 10 OR2 4 0 1 0 :70
- 2 - A 10 OR2 4 0 1 0 :71
- 1 - A 10 OR2 4 0 1 0 :72
- 3 - A 10 OR2 4 0 1 0 :73
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\kejian\zong\verilog\modsel.rpt
modsel
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 7/ 48( 14%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\kejian\zong\verilog\modsel.rpt
modsel
** EQUATIONS **
da11 : INPUT;
da12 : INPUT;
da13 : INPUT;
da14 : INPUT;
da15 : INPUT;
da16 : INPUT;
da17 : INPUT;
da30 : INPUT;
da31 : INPUT;
da32 : INPUT;
da33 : INPUT;
da34 : INPUT;
da35 : INPUT;
da36 : INPUT;
da37 : INPUT;
ModSel0 : INPUT;
ModSel1 : INPUT;
-- Node name is 'da_out0'
-- Equation name is 'da_out0', type is output
da_out0 = _LC3_A10;
-- Node name is 'da_out1'
-- Equation name is 'da_out1', type is output
da_out1 = _LC1_A10;
-- Node name is 'da_out2'
-- Equation name is 'da_out2', type is output
da_out2 = _LC2_A10;
-- Node name is 'da_out3'
-- Equation name is 'da_out3', type is output
da_out3 = _LC8_A10;
-- Node name is 'da_out4'
-- Equation name is 'da_out4', type is output
da_out4 = _LC4_A10;
-- Node name is 'da_out5'
-- Equation name is 'da_out5', type is output
da_out5 = _LC5_A10;
-- Node name is 'da_out6'
-- Equation name is 'da_out6', type is output
da_out6 = _LC6_A10;
-- Node name is 'da_out7'
-- Equation name is 'da_out7', type is output
da_out7 = _LC7_A10;
-- Node name is ':46'
-- Equation name is '_LC7_A10', type is buried
_LC7_A10 = LCELL( _EQ001);
_EQ001 = da37 & !ModSel0 & ModSel1;
-- Node name is ':67'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = LCELL( _EQ002);
_EQ002 = da17 & !ModSel0 & !ModSel1
# da36 & !ModSel0 & ModSel1;
-- Node name is ':68'
-- Equation name is '_LC5_A10', type is buried
_LC5_A10 = LCELL( _EQ003);
_EQ003 = da16 & !ModSel0 & !ModSel1
# da35 & !ModSel0 & ModSel1;
-- Node name is ':69'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = LCELL( _EQ004);
_EQ004 = da15 & !ModSel0 & !ModSel1
# da34 & !ModSel0 & ModSel1;
-- Node name is ':70'
-- Equation name is '_LC8_A10', type is buried
_LC8_A10 = LCELL( _EQ005);
_EQ005 = da14 & !ModSel0 & !ModSel1
# da33 & !ModSel0 & ModSel1;
-- Node name is ':71'
-- Equation name is '_LC2_A10', type is buried
_LC2_A10 = LCELL( _EQ006);
_EQ006 = da13 & !ModSel0 & !ModSel1
# da32 & !ModSel0 & ModSel1;
-- Node name is ':72'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ007);
_EQ007 = da12 & !ModSel0 & !ModSel1
# da31 & !ModSel0 & ModSel1;
-- Node name is ':73'
-- Equation name is '_LC3_A10', type is buried
_LC3_A10 = LCELL( _EQ008);
_EQ008 = da11 & !ModSel0 & !ModSel1
# da30 & !ModSel0 & ModSel1;
Project Information c:\kejian\zong\verilog\modsel.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,416K
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