tst1.twr

Verilog编程

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml TST1 TST1.ncd -o
TST1.twr TST1.pcf


Design file:              TST1.ncd
Physical constraint file: TST1.pcf
Device,speed:             xc3s400,-4 (PREVIEW 1.26 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
clk            |out            |    8.345|
---------------+---------------+---------+

Analysis completed Tue May 08 22:45:20 2007
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Peak Memory Usage: 56 MB