ding_tbw.ant

Verilog编程

// E:\ISE6.1\TST
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Sun May 06 16:32:39 2007

`timescale 1ns/1ns

`define s0	0
`define F_ASSERT	2
`define OD	4
`define s4	4
`define FDEPTH	4
`define BR0	0
`define F_IDLE	1
`define s2	2
`define C_WRITE	4
`define F_DEASSERT	4
`define state_delay	6
`define N	5
`define Q	25
`define C_REFRSH	1
`define D	10
`define IF2	3
`define C_ACTIVE	3
`define C_READ	5
`define FWIDTH	32
`define FCWIDTH	2
`define s3	3
`define s1	1
`define C_NOP	7
`define C_L_MODE	0
`define C_P_CHRG	2
`define TCKO	0
`define RES	5
`define IF0	1
`define IF2	3
`define IF1	2
`define C_NOP	7
`define D	10
`define C_READ	5
`define C_ACTIVE	3
`define F_IDLE	1
`define F_IDLE	1
`define F_ASSERT	2

module ding_tbw;
	reg clkin;
	reg rst;
	reg NCS0_n;
	reg NWE_n;
	reg [4:0] addr;
	reg [15:0] DataIN;
	wire [7:0] SINE1;
	wire [7:0] SINE2;
	wire [7:0] SINE3;
	wire [7:0] SINE4;
	wire [7:0] SINE5;
	wire [7:0] SINE6;
	wire clk_out;

	defparam UUT.wordwidth_data = 16;
	defparam UUT.memsize_data = 32;

	top UUT (
		.clkin(clkin),
		.rst(rst),
		.NCS0_n(NCS0_n),
		.NWE_n(NWE_n),
		.addr(addr),
		.DataIN(DataIN),
		.SINE1(SINE1),
		.SINE2(SINE2),
		.SINE3(SINE3),
		.SINE4(SINE4),
		.SINE5(SINE5),
		.SINE6(SINE6),
		.clk_out(clk_out)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clkin = 1'b0;
	#2
	clkin = 1'b1;
	#2
	ANNOTATE_SINE1;
	ANNOTATE_SINE2;
	ANNOTATE_SINE3;
	ANNOTATE_SINE4;
	ANNOTATE_SINE5;
	ANNOTATE_SINE6;
	ANNOTATE_clk_out;
	#8
	clkin = 1'b0;
	#8
	clkin = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("e:\\ise6.1\\tst\\ding_tbw.ano");

	// --------------------
	rst = 1'b0;
	NCS0_n = 1'b1;
	NWE_n = 1'b1;
	addr = 5'b00000; //0
	DataIN = 16'b0000000000000000; //0
	// --------------------
	#20 // Time=20 ns
	rst = 1'b1;
	// --------------------
	#40 // Time=60 ns
	rst = 1'b0;
	// --------------------
	#360 // Time=420 ns
	NCS0_n = 1'b0;
	addr = 5'b00010; //2
	// --------------------
	#20 // Time=440 ns
	NWE_n = 1'b0;
	addr = 5'b00010; //2
	DataIN = 16'b0000111111111111; //FFF
	// --------------------
	#20 // Time=460 ns
	NWE_n = 1'b1;
	addr = 5'b00010; //2
	DataIN = 16'b0000111111111111; //FFF
	// --------------------
	#4 // Time=464 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_SINE1;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SINE1,%b]",
			$time, SINE1);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_SINE2;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SINE2,%b]",
			$time, SINE2);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_SINE3;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SINE3,%b]",
			$time, SINE3);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_SINE4;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SINE4,%b]",
			$time, SINE4);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_SINE5;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SINE5,%b]",
			$time, SINE5);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_SINE6;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SINE6,%b]",
			$time, SINE6);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_clk_out;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,clk_out,%b]",
			$time, clk_out);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule