dds4.syr

Verilog编程

  Source Clock:      DDS50_counterclk_outclktemp:Q rising
  Destination Clock: DDS50_counterclk_outclktemp:Q rising

  Data Path: DDS50_PHA_ACC_t1_0 to DDS50_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  DDS50_PHA_ACC_t1_0 (DDS50_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (DDS50_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_0 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_1 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_2 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_3 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_4 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_5 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_6 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_7 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_8 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_9 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_10 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_11 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_12 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_13 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_14 (DDS50_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  DDS50_PHA_ACC_t1_Madd__n0000_inst_sum_15 (DDS50_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          DDS50_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DDS40_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            DDS40_PHA_ACC_t1_0 (FF)
  Destination:       DDS40_PHA_ACC_t1_15 (FF)
  Source Clock:      DDS40_counterclk_outclktemp:Q rising
  Destination Clock: DDS40_counterclk_outclktemp:Q rising

  Data Path: DDS40_PHA_ACC_t1_0 to DDS40_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  DDS40_PHA_ACC_t1_0 (DDS40_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (DDS40_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_0 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_1 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_2 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_3 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_4 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_5 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_6 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_7 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_8 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_9 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_10 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_11 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_12 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_13 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_14 (DDS40_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  DDS40_PHA_ACC_t1_Madd__n0000_inst_sum_15 (DDS40_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          DDS40_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DDS30_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            DDS30_PHA_ACC_t1_0 (FF)
  Destination:       DDS30_PHA_ACC_t1_15 (FF)
  Source Clock:      DDS30_counterclk_outclktemp:Q rising
  Destination Clock: DDS30_counterclk_outclktemp:Q rising

  Data Path: DDS30_PHA_ACC_t1_0 to DDS30_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  DDS30_PHA_ACC_t1_0 (DDS30_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (DDS30_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_0 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_1 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_2 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_3 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_4 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_5 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_6 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_7 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_8 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_9 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_10 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_11 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_12 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_13 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_14 (DDS30_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  DDS30_PHA_ACC_t1_Madd__n0000_inst_sum_15 (DDS30_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          DDS30_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DDS20_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            DDS20_PHA_ACC_t1_0 (FF)
  Destination:       DDS20_PHA_ACC_t1_15 (FF)
  Source Clock:      DDS20_counterclk_outclktemp:Q rising
  Destination Clock: DDS20_counterclk_outclktemp:Q rising

  Data Path: DDS20_PHA_ACC_t1_0 to DDS20_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  DDS20_PHA_ACC_t1_0 (DDS20_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (DDS20_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_0 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_1 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_2 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_3 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_4 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_5 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_6 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_7 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_8 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_9 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_10 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_11 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_12 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_13 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_14 (DDS20_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  DDS20_PHA_ACC_t1_Madd__n0000_inst_sum_15 (DDS20_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          DDS20_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DDS10_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            DDS10_PHA_ACC_t1_0 (FF)
  Destination:       DDS10_PHA_ACC_t1_15 (FF)
  Source Clock:      DDS10_counterclk_outclktemp:Q rising
  Destination Clock: DDS10_counterclk_outclktemp:Q rising

  Data Path: DDS10_PHA_ACC_t1_0 to DDS10_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  DDS10_PHA_ACC_t1_0 (DDS10_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (DDS10_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_0 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_1 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_2 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_3 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_4 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_5 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_6 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_7 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_8 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_9 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_10 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_11 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_12 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_13 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_14 (DDS10_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  DDS10_PHA_ACC_t1_Madd__n0000_inst_sum_15 (DDS10_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          DDS10_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK0'
Offset:              2.234ns (Levels of Logic = 1)
  Source:            CONTROL<4> (PAD)
  Destination:       WE6 (FF)
  Destination Clock: CLK0 rising

  Data Path: CONTROL<4> to WE6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.492   0.240  CONTROL_4_IBUF (CONTROL_4_IBUF)
     FDC:D                     0.502          WE6
    ----------------------------------------
    Total                      2.234ns (1.994ns logic, 0.240ns route)
                                       (89.3% logic, 10.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK0'
Offset:              9.161ns (Levels of Logic = 2)
  Source:            DDS10_rom/B5 (RAM)
  Destination:       SINE1<7> (PAD)
  Source Clock:      CLK0 rising

  Data Path: DDS10_rom/B5 to SINE1<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S9:CLK->DO7    1   3.509   0.240  B5 (dout<7>)
     end scope: 'DDS10_rom'
     OBUF:I->O                 5.412          SINE1_7_OBUF (SINE1<7>)
    ----------------------------------------
    Total                      9.161ns (8.921ns logic, 0.240ns route)
                                       (97.4% logic, 2.6% route)

=========================================================================
CPU : 23.62 / 24.64 s | Elapsed : 24.00 / 25.00 s
 
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Total memory usage is 79912 kilobytes