dds4.syr

Verilog编程

Optimizing unit <DDS1> ...
Loading device for application Xst from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dds4, actual ratio is 17.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : dds4.ngr
Top Level Output File Name         : dds4
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 354

Macro Statistics :
# Registers                        : 54
#      1-bit register              : 18
#      16-bit register             : 36
# Counters                         : 6
#      26-bit up counter           : 6
# Adders/Subtractors               : 24
#      16-bit adder                : 24
# Comparators                      : 12
#      28-bit comparator greatequal: 6
#      32-bit comparator greatequal: 6

Cell Usage :
# BELS                             : 2007
#      BUF                         : 1
#      GND                         : 7
#      LUT1                        : 84
#      LUT1_L                      : 78
#      LUT2                        : 288
#      LUT2_L                      : 258
#      LUT3                        : 6
#      LUT3_L                      : 6
#      LUT4                        : 30
#      LUT4_L                      : 30
#      MUXCY                       : 744
#      VCC                         : 1
#      XORCY                       : 474
# FlipFlops/Latches                : 702
#      FDC                         : 252
#      FDCE                        : 288
#      FDCPE                       : 156
#      FDP                         : 6
# RAMS                             : 6
#      RAMB16_S9                   : 6
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 349
#      IBUF                        : 301
#      OBUF                        : 48
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     617  out of   3584    17%  
 Number of Slice Flip Flops:           702  out of   7168     9%  
 Number of 4 input LUTs:               780  out of   7168    10%  
 Number of bonded IOBs:                349  out of    141   247% (*) 
 Number of BRAMs:                        6  out of      8    75%  
 Number of GCLKs:                        1  out of      8    12%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK0                               | BUFGP                  | 612   |
DDS60_counterclk_outclktemp:Q      | NONE                   | 16    |
DDS50_counterclk_outclktemp:Q      | NONE                   | 16    |
DDS40_counterclk_outclktemp:Q      | NONE                   | 16    |
DDS30_counterclk_outclktemp:Q      | NONE                   | 16    |
DDS20_counterclk_outclktemp:Q      | NONE                   | 16    |
DDS10_counterclk_outclktemp:Q      | NONE                   | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.693ns (Maximum Frequency: 93.519MHz)
   Minimum input arrival time before clock: 2.234ns
   Maximum output required time after clock: 9.161ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK0'
Delay:               10.693ns (Levels of Logic = 47)
  Source:            DDS60_counterclk_cout_0 (FF)
  Destination:       DDS60_counterclk_cout_25 (FF)
  Source Clock:      CLK0 rising
  Destination Clock: CLK0 rising

  Data Path: DDS60_counterclk_cout_0 to DDS60_counterclk_cout_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            3   0.619   0.577  DDS60_counterclk_cout_0 (DDS60_counterclk_cout_0)
     LUT4_L:I0->LO         1   0.720   0.000  DDS60_counterclk_Mcompar__n0002_inst_lut4_61 (DDS60_counterclk_Mcompar__n0002_inst_lut4_6)
     MUXCY:S->O            1   0.629   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_35 (DDS60_counterclk_Mcompar__n0002_inst_cy_35)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_36 (DDS60_counterclk_Mcompar__n0002_inst_cy_36)
     MUXCY:CI->O           1   0.091   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_37 (DDS60_counterclk_Mcompar__n0002_inst_cy_37)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_38 (DDS60_counterclk_Mcompar__n0002_inst_cy_38)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_39 (DDS60_counterclk_Mcompar__n0002_inst_cy_39)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_40 (DDS60_counterclk_Mcompar__n0002_inst_cy_40)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_41 (DDS60_counterclk_Mcompar__n0002_inst_cy_41)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_42 (DDS60_counterclk_Mcompar__n0002_inst_cy_42)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_43 (DDS60_counterclk_Mcompar__n0002_inst_cy_43)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_44 (DDS60_counterclk_Mcompar__n0002_inst_cy_44)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_45 (DDS60_counterclk_Mcompar__n0002_inst_cy_45)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_46 (DDS60_counterclk_Mcompar__n0002_inst_cy_46)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_47 (DDS60_counterclk_Mcompar__n0002_inst_cy_47)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_48 (DDS60_counterclk_Mcompar__n0002_inst_cy_48)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_49 (DDS60_counterclk_Mcompar__n0002_inst_cy_49)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_50 (DDS60_counterclk_Mcompar__n0002_inst_cy_50)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_Mcompar__n0002_inst_cy_51 (DDS60_counterclk_Mcompar__n0002_inst_cy_51)
     MUXCY:CI->O          28   0.331   1.317  DDS60_counterclk_Mcompar__n0002_inst_cy_52 (DDS60_counterclk_Mcompar__n0002_inst_cy_52)
     LUT1_L:I0->LO         1   0.720   0.000  DDS60_counterclk__n0002_rt (DDS60_counterclk__n0002_rt)
     MUXCY:S->O            1   0.629   0.000  DDS60_counterclk_cout_inst_cy_55 (DDS60_counterclk_cout_inst_cy_55)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_56 (DDS60_counterclk_cout_inst_cy_56)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_57 (DDS60_counterclk_cout_inst_cy_57)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_58 (DDS60_counterclk_cout_inst_cy_58)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_59 (DDS60_counterclk_cout_inst_cy_59)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_60 (DDS60_counterclk_cout_inst_cy_60)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_61 (DDS60_counterclk_cout_inst_cy_61)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_62 (DDS60_counterclk_cout_inst_cy_62)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_63 (DDS60_counterclk_cout_inst_cy_63)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_64 (DDS60_counterclk_cout_inst_cy_64)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_65 (DDS60_counterclk_cout_inst_cy_65)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_66 (DDS60_counterclk_cout_inst_cy_66)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_67 (DDS60_counterclk_cout_inst_cy_67)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_68 (DDS60_counterclk_cout_inst_cy_68)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_69 (DDS60_counterclk_cout_inst_cy_69)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_70 (DDS60_counterclk_cout_inst_cy_70)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_71 (DDS60_counterclk_cout_inst_cy_71)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_72 (DDS60_counterclk_cout_inst_cy_72)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_73 (DDS60_counterclk_cout_inst_cy_73)
     MUXCY:CI->O           1   0.091   0.000  DDS60_counterclk_cout_inst_cy_74 (DDS60_counterclk_cout_inst_cy_74)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_75 (DDS60_counterclk_cout_inst_cy_75)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_76 (DDS60_counterclk_cout_inst_cy_76)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_77 (DDS60_counterclk_cout_inst_cy_77)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_78 (DDS60_counterclk_cout_inst_cy_78)
     MUXCY:CI->O           1   0.090   0.000  DDS60_counterclk_cout_inst_cy_79 (DDS60_counterclk_cout_inst_cy_79)
     MUXCY:CI->O           0   0.090   0.000  DDS60_counterclk_cout_inst_cy_80 (DDS60_counterclk_cout_inst_cy_80)
     XORCY:CI->O           1   0.939   0.000  DDS60_counterclk_cout_inst_sum_41 (DDS60_counterclk_cout_inst_sum_41)
     FDCPE:D                   0.502          DDS60_counterclk_cout_25
    ----------------------------------------
    Total                     10.693ns (8.799ns logic, 1.894ns route)
                                       (82.3% logic, 17.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DDS60_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            DDS60_PHA_ACC_t1_0 (FF)
  Destination:       DDS60_PHA_ACC_t1_15 (FF)
  Source Clock:      DDS60_counterclk_outclktemp:Q rising
  Destination Clock: DDS60_counterclk_outclktemp:Q rising

  Data Path: DDS60_PHA_ACC_t1_0 to DDS60_PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  DDS60_PHA_ACC_t1_0 (DDS60_PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_lut2_01 (DDS60_PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_0 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_1 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_2 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_3 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_4 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_5 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_6 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_7 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_8 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_9 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_10 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_11 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_12 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_13 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_14 (DDS60_PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  DDS60_PHA_ACC_t1_Madd__n0000_inst_sum_15 (DDS60_PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          DDS60_PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'DDS50_counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            DDS50_PHA_ACC_t1_0 (FF)
  Destination:       DDS50_PHA_ACC_t1_15 (FF)