dds4.syr

Verilog编程

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.62 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.62 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: dds4.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : dds4.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : dds4
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : dds4
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : dds4.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:Xst:878 - rom1.v line 98: Unrecognized directive. Ignoring.
Compiling source file "counter.v"
Module <counter> compiled
Compiling source file "rom1.v"
Module <rom1> compiled
Compiling source file "DDS1.v"
Module <DDS1> compiled
Compiling source file "dds4.v"
Module <dds4> compiled
No errors in compilation
Analysis of file <dds4.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <dds4>.
Module <dds4> is correct for synthesis.
 
Analyzing module <DDS1>.
Module <DDS1> is correct for synthesis.
 
Analyzing module <counter>.
WARNING:Xst:854 - counter.v line 10: Ignored initial statement.
Module <counter> is correct for synthesis.
 
Analyzing module <rom1>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is counter.v.
    Found 28-bit comparator greatequal for signal <$n0002> created at line 27.
    Found 32-bit comparator greatequal for signal <$n0004> created at line 32.
    Found 26-bit up counter for signal <cout>.
    Found 1-bit register for signal <outclktemp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <counter> synthesized.


Synthesizing Unit <DDS1>.
    Related source file is DDS1.v.
WARNING:Xst:646 - Signal <acc<7:0>> is assigned but never used.
    Found 16-bit adder for signal <$n0001> created at line 73.
    Found 16-bit adder for signal <$n0002>.
    Found 16-bit register for signal <acc>.
    Found 16-bit up accumulator for signal <acc_t>.
    Found 16-bit register for signal <DATA_FRE_t>.
    Found 16-bit register for signal <DATA_PHA_t>.
    Found 16-bit register for signal <PHA_ACC_t>.
    Found 16-bit up accumulator for signal <PHA_ACC_t1>.
    Summary:
	inferred   2 Accumulator(s).
	inferred  64 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <DDS1> synthesized.


Synthesizing Unit <dds4>.
    Related source file is dds4.v.
WARNING:Xst:647 - Input <CONTROL<3:0>> is never used.
    Found 1-bit register for signal <SCLR1>.
    Found 1-bit register for signal <SCLR2>.
    Found 1-bit register for signal <SCLR3>.
    Found 1-bit register for signal <SCLR4>.
    Found 1-bit register for signal <SCLR5>.
    Found 1-bit register for signal <SCLR6>.
    Found 1-bit register for signal <WE1>.
    Found 1-bit register for signal <WE2>.
    Found 1-bit register for signal <WE3>.
    Found 1-bit register for signal <WE4>.
    Found 1-bit register for signal <WE5>.
    Found 1-bit register for signal <WE6>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <dds4> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 42
  1-bit register                   : 18
  16-bit register                  : 24
# Counters                         : 6
  26-bit up counter                : 6
# Accumulators                     : 12
  16-bit up accumulator            : 12
# Adders/Subtractors               : 12
  16-bit adder                     : 12
# Comparators                      : 12
  28-bit comparator greatequal     : 6
  32-bit comparator greatequal     : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "rom1.ngo" is up to date.
Loading core <rom1> for timing and area information for instance <rom>.
WARNING:Xst:1291 - FF/Latch <acc_0> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_1> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_2> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_3> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_4> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_5> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_6> is unconnected in block <DDS1>.
WARNING:Xst:1291 - FF/Latch <acc_7> is unconnected in block <DDS1>.

Optimizing unit <dds4> ...