tst.par

来自「Verilog编程」· PAR 代码 · 共 120 行

Release 6.1i Par G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

DWS::  Sat Apr 28 11:06:43 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 tst_map.ncd tst.ncd
tst.pcf 


Constraints file: tst.pcf

Loading device database for application Par from file "tst_map.ncd".
   "tst" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
C:/Xilinx.
Device speed data version:  PREVIEW 1.27 2003-11-04.


Device utilization summary:

   Number of External IOBs            40 out of 141    28%
      Number of LOCed External IOBs    0 out of 40      0%

   Number of Slices                   46 out of 3600    1%
      Number of RAMB16s                1 out of 16      6%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897b0) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
....
Phase 5.8 (Checksum:9b0eb9) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file tst.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 355 unrouted;       REAL time: 3 secs 

Phase 2: 290 unrouted;       REAL time: 4 secs 

Phase 3: 47 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX0| No   |   58 |  0.110     |  0.458      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 158


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.083
   The MAXIMUM PIN DELAY IS:                               3.262
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.467

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         186         112          54           3           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  67 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file tst.ncd.


PAR done.