top.drc

来自「Verilog编程」· DRC 代码 · 共 39 行

DRC
39 行
字号 
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<10> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<0> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<1> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<2> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<3> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<4> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<5> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<6> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<7> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<8> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<9> is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out1 is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out2 is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out3 is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out4 is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out5 is set but TMUX is not configured.WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out6 is set but TMUX is not configured.INFO:DesignRules:547 - Blockcheck: To achieve optimal frequency synthesis
   performance with the CLKFX and CLKFX180 outputs of the DCM comp
   instance_name_DCM_INST, consult the Virtex-II Interactive Data Sheet.DRC detected 0 errors and 17 warnings.

top.drc - 源码说明

本页面展示了「Verilog编程」中的 top.drc 源码文件，采用 DRC 编程语言编写，共 39 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫下载站收录了大量与Verilog相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?