armtst.twr

来自「Verilog编程」· TWR 代码 · 共 101 行

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Release 6.1i Trace G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml armtst armtst.ncd -o
armtst.twr armtst.pcf


Design file:              armtst.ncd
Physical constraint file: armtst.pcf
Device,speed:             xc3s400,-4 (PREVIEW 1.27 2003-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock NWE_n
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
DataIN<0>   |    2.751(R)|    0.948(R)|NWE_n_BUFGP       |   0.000|
DataIN<10>  |    3.117(R)|    0.495(R)|NWE_n_BUFGP       |   0.000|
DataIN<11>  |    3.462(R)|    0.369(R)|NWE_n_BUFGP       |   0.000|
DataIN<12>  |    3.409(R)|    0.899(R)|NWE_n_BUFGP       |   0.000|
DataIN<13>  |    3.899(R)|    0.389(R)|NWE_n_BUFGP       |   0.000|
DataIN<14>  |    3.085(R)|    0.923(R)|NWE_n_BUFGP       |   0.000|
DataIN<15>  |    3.653(R)|    0.378(R)|NWE_n_BUFGP       |   0.000|
DataIN<1>   |    3.435(R)|    0.842(R)|NWE_n_BUFGP       |   0.000|
DataIN<2>   |    3.533(R)|    0.253(R)|NWE_n_BUFGP       |   0.000|
DataIN<3>   |    3.235(R)|    0.713(R)|NWE_n_BUFGP       |   0.000|
DataIN<4>   |    2.954(R)|    0.853(R)|NWE_n_BUFGP       |   0.000|
DataIN<5>   |    3.343(R)|    0.389(R)|NWE_n_BUFGP       |   0.000|
DataIN<6>   |    3.178(R)|    0.509(R)|NWE_n_BUFGP       |   0.000|
DataIN<7>   |    3.540(R)|    0.608(R)|NWE_n_BUFGP       |   0.000|
DataIN<8>   |    3.013(R)|    0.691(R)|NWE_n_BUFGP       |   0.000|
DataIN<9>   |    3.028(R)|    0.597(R)|NWE_n_BUFGP       |   0.000|
NCS3_n      |    4.091(R)|    0.922(R)|NWE_n_BUFGP       |   0.000|
addr<0>     |    8.339(R)|    0.021(R)|NWE_n_BUFGP       |   0.000|
addr<1>     |    8.971(R)|   -0.391(R)|NWE_n_BUFGP       |   0.000|
addr<2>     |    7.629(R)|    0.315(R)|NWE_n_BUFGP       |   0.000|
addr<3>     |    7.501(R)|   -0.219(R)|NWE_n_BUFGP       |   0.000|
addr<4>     |    6.995(R)|   -0.221(R)|NWE_n_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clkin to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
out<0>      |    7.414(R)|CLK0              |   0.000|
out<10>     |    7.421(R)|CLK0              |   0.000|
out<11>     |    7.421(R)|CLK0              |   0.000|
out<12>     |    7.421(R)|CLK0              |   0.000|
out<13>     |    7.421(R)|CLK0              |   0.000|
out<14>     |    7.422(R)|CLK0              |   0.000|
out<15>     |    7.422(R)|CLK0              |   0.000|
out<1>      |    7.421(R)|CLK0              |   0.000|
out<2>      |    7.421(R)|CLK0              |   0.000|
out<3>      |    7.421(R)|CLK0              |   0.000|
out<4>      |    7.421(R)|CLK0              |   0.000|
out<5>      |    7.421(R)|CLK0              |   0.000|
out<6>      |    7.421(R)|CLK0              |   0.000|
out<7>      |    7.421(R)|CLK0              |   0.000|
out<8>      |    7.421(R)|CLK0              |   0.000|
out<9>      |    7.415(R)|CLK0              |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock NWE_n
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
NWE_n          |   10.459|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock clkin
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
NWE_n          |    5.767|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sat Apr 28 19:33:18 2007
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Peak Memory Usage: 62 MB