core.tpl

来自「Verilog编程」· TPL 代码 · 共 201 行

[COREGEN.VERILOG Component Instantiation.fifo_asyn]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="fifo_asyn YourInstanceName ("
text007="    .din(din),"
text008="    .wr_en(wr_en),"
text009="    .wr_clk(wr_clk),"
text010="    .rd_en(rd_en),"
text011="    .rd_clk(rd_clk),"
text012="    .ainit(ainit),"
text013="    .dout(dout),"
text014="    .full(full),"
text015="    .empty(empty));"
text016=""
text017=" "
type=template
[COREGEN.VERILOG Component Instantiation.ram]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="ram YourInstanceName ("
text007="    .addra(addra),"
text008="    .addrb(addrb),"
text009="    .clka(clka),"
text010="    .clkb(clkb),"
text011="    .dina(dina),"
text012="    .doutb(doutb),"
text013="    .ena(ena),"
text014="    .wea(wea));"
text015=""
text016=" "
type=template
[COREGEN.VERILOG Component Instantiation.rom]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="rom YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .dout(dout));"
text010=""
text011=" "
type=template
[COREGEN.VERILOG Component Instantiation.rom1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="rom1 YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .dout(dout),"
text010="    .en(en));"
text011=""
text012=" "
type=template
[COREGEN.VHDL Component Instantiation.fifo_asyn]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component fifo_asyn"
text005="    port ("
text006="    din: IN std_logic_VECTOR(15 downto 0);"
text007="    wr_en: IN std_logic;"
text008="    wr_clk: IN std_logic;"
text009="    rd_en: IN std_logic;"
text010="    rd_clk: IN std_logic;"
text011="    ainit: IN std_logic;"
text012="    dout: OUT std_logic_VECTOR(15 downto 0);"
text013="    full: OUT std_logic;"
text014="    empty: OUT std_logic);"
text015="end component;"
text016=""
text017=""
text018=""
text019=" "
text020="-------------------------------------------------------------"
text021=" "
text022="-- The following code must appear in the VHDL architecture body."
text023="-- Substitute your own instance name and net names."
text024=" "
text025="your_instance_name : fifo_asyn"
text026="        port map ("
text027="            din => din,"
text028="            wr_en => wr_en,"
text029="            wr_clk => wr_clk,"
text030="            rd_en => rd_en,"
text031="            rd_clk => rd_clk,"
text032="            ainit => ainit,"
text033="            dout => dout,"
text034="            full => full,"
text035="            empty => empty);"
text036=" "
type=template
[COREGEN.VHDL Component Instantiation.ram]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component ram"
text005="    port ("
text006="    addra: IN std_logic_VECTOR(3 downto 0);"
text007="    addrb: IN std_logic_VECTOR(3 downto 0);"
text008="    clka: IN std_logic;"
text009="    clkb: IN std_logic;"
text010="    dina: IN std_logic_VECTOR(15 downto 0);"
text011="    doutb: OUT std_logic_VECTOR(15 downto 0);"
text012="    ena: IN std_logic;"
text013="    wea: IN std_logic);"
text014="end component;"
text015=""
text016=""
text017=""
text018=" "
text019="-------------------------------------------------------------"
text020=" "
text021="-- The following code must appear in the VHDL architecture body."
text022="-- Substitute your own instance name and net names."
text023=" "
text024="your_instance_name : ram"
text025="        port map ("
text026="            addra => addra,"
text027="            addrb => addrb,"
text028="            clka => clka,"
text029="            clkb => clkb,"
text030="            dina => dina,"
text031="            doutb => doutb,"
text032="            ena => ena,"
text033="            wea => wea);"
text034=" "
type=template
[COREGEN.VHDL Component Instantiation.rom]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component rom"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(7 downto 0);"
text007="    clk: IN std_logic;"
text008="    dout: OUT std_logic_VECTOR(15 downto 0));"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : rom"
text020="        port map ("
text021="            addr => addr,"
text022="            clk => clk,"
text023="            dout => dout);"
text024=" "
type=template
[COREGEN.VHDL Component Instantiation.rom1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component rom1"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(10 downto 0);"
text007="    clk: IN std_logic;"
text008="    dout: OUT std_logic_VECTOR(10 downto 0);"
text009="    en: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : rom1"
text021="        port map ("
text022="            addr => addr,"
text023="            clk => clk,"
text024="            dout => dout,"
text025="            en => en);"
text026=" "
type=template