coregen.log

Verilog编程

# Xilinx CORE Generator 6.1.03i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in D:\商共享资料\程序\两路正弦波\coregen.log
# lockprojectprops=false
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=D:\商共享资料\程序\两路正弦波
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=Verilog VHDL
# xilinxfamily=Spartan3
# outputoption=OutputProducts
# overwritefiles=true
# simvendor=ModelSim
# expandedprojectpath=D:\商共享资料\程序\两路正弦波
SETPROJECT .
Set current Project to D:\商共享资料\程序\两路正弦波
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1937
XIPCPJSENDCORES spartan3