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Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
C:/Xilinx.
Device speed data version:  PREVIEW 1.26 2003-06-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            92 out of 141    65%
      Number of LOCed External IOBs   91 out of 92     98%

   Number of MULT18X18s                6 out of 16     37%
   Number of RAMB16s                   6 out of 16     37%
   Number of SLICELs                1076 out of 3584   30%
   Number of SLICEMs                  64 out of 1792    3%

   Number of BUFGMUXs                  3 out of 8      37%
   Number of DCMs                      1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98b85b) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
.....................
Phase 5.8 (Checksum:b23067) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 5 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 5 secs 
Total CPU time to Placer completion: 4 secs 


Phase 1: 7011 unrouted;       REAL time: 6 secs 

Phase 2: 6110 unrouted;       REAL time: 6 secs 

Phase 3: 2052 unrouted;       REAL time: 7 secs 

Phase 4: 0 unrouted;       REAL time: 10 secs 

Total REAL time to Router completion: 10 secs 
Total CPU time to Router completion: 8 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         CLKDV_OUT       |  BUFGMUX2| No   |  332 |  0.161     |  0.460      |
+-------------------------+----------+------+------+------------+-------------+
|              CLK0       |  BUFGMUX0| No   |  159 |  0.088     |  0.387      |
+-------------------------+----------+------+------+------------+-------------+
|       NWE_n_BUFGP       |  BUFGMUX1| No   |  257 |  0.105     |  0.410      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS10_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.740     |  2.596      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS30_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.042     |  2.112      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS20_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.053     |  1.736      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS60_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.063     |  2.151      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS50_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    9 |  0.042     |  2.078      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS40_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.061     |  2.496      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 11 secs 
Total CPU time to PAR completion: 9 secs 

Peak Memory Usage:  80 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Sun Nov 25 19:48:15 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
PAR completed successfully




Started process "Programming File Generation Report".

Completed process "Programming File Generation Report".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View HDL Source".

Release 6.1i - xaw2verilog G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
xaw2verilog: Completed successfully
Completed process "View HDL Source".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:Xst:878 - rom1.v line 98: Unrecognized directive. Ignoring.
Compiling source file "my_dcm1.v"
Module <my_dcm1> compiled
Compiling source file "counter.v"
Module <counter> compiled
Compiling source file "rom1.v"
Module <rom1> compiled
Compiling source file "DDS1.v"
Module <DDS1> compiled
Compiling source file "dds4.v"
Module <dds4> compiled
Compiling source file "top.v"
Module <top> compiled
No errors in compilation
Analysis of file <top.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
WARNING:HDLCompilers:259 - DDS1.v line 102 Connection to input port 'addr' does not match port size
Analyzing top module <top>.
Module <top> is correct for synthesis.
 
Analyzing module <my_dcm1>.
Module <my_dcm1> is correct for synthesis.
 
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKDV_DIVIDE =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKFX_DIVIDE =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKIN_PERIOD =  20" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <my_dcm1>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <my_dcm1>.
Analyzing module <DCM>.
Analyzing module <IBUFG>.
Analyzing module <BUFG>.
Analyzing module <dds4>.
Module <dds4> is correct for synthesis.
 
Analyzing module <DDS1>.
Module <DDS1> is correct for synthesis.
 
Analyzing module <counter>.
WARNING:Xst:854 - counter.v line 10: Ignored initial statement.
Module <counter> is correct for synthesis.
 
Analyzing module <rom1>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is counter.v.
    Found 28-bit comparator greatequal for signal <$n0002> created at line 27.
    Found 32-bit comparator greatequal for signal <$n0004> created at line 32.
    Found 26-bit up counter for signal <cout>.
    Found 1-bit register for signal <outclktemp>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <counter> synthesized.


Synthesizing Unit <DDS1>.
    Related source file is DDS1.v.
WARNING:Xst:646 - Signal <acc<4:0>> is assigned but never used.
WARNING:Xst:643 - The result of a 11x3-bit multiplication found at line 107 is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 16-bit adder for signal <$n0003> created at line 76.
    Found 1-bit adder for signal <$n0005> created at line 107.
    Found 3-bit subtractor for signal <$n0007> created at line 107.
    Found 16-bit adder for signal <$n0008>.
    Found 11x3-bit multiplier for signal <$n0009> created at line 107.
    Found 16-bit register for signal <acc>.
    Found 16-bit up accumulator for signal <acc_t>.
    Found 16-bit register for signal <DATA_FRE_t>.
    Found 16-bit register for signal <DATA_PHA_t>.
    Found 2-bit register for signal <flag>.
    Found 16-bit register for signal <PHA_ACC_t>.
    Found 16-bit up accumulator for signal <PHA_ACC_t1>.
    Summary:
	inferred   2 Accumulator(s).
	inferred  66 D-type flip-flop(s).
	inferred   4 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <DDS1> synthesized.


Synthesizing Unit <dds4>.
    Related source file is dds4.v.
WARNING:Xst:647 - Input <CONTROL<3:0>> is never used.
    Found 1-bit register for signal <SCLR1>.
    Found 1-bit register for signal <SCLR2>.
    Found 1-bit register for signal <SCLR3>.
    Found 1-bit register for signal <SCLR4>.
    Found 1-bit register for signal <SCLR5>.
    Found 1-bit register for signal <SCLR6>.
    Found 1-bit register for signal <WE1>.
    Found 1-bit register for signal <WE2>.
    Found 1-bit register for signal <WE3>.
    Found 1-bit register for signal <WE4>.
    Found 1-bit register for signal <WE5>.
    Found 1-bit register for signal <WE6>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <dds4> synthesized.


Synthesizing Unit <my_dcm1>.
    Related source file is my_dcm1.v.
Unit <my_dcm1> synthesized.


Synthesizing Unit <top>.
    Related source file is top.v.
    Found 16-bit 32-to-1 multiplexer for signal <$COND_1>.
    Found 16-bit register for signal <CONTROL>.
    Found 16-bit register for signal <DATA_FRE1>.
    Found 16-bit register for signal <DATA_FRE2>.
    Found 16-bit register for signal <DATA_FRE3>.
    Found 16-bit register for signal <DATA_FRE4>.
    Found 16-bit register for signal <DATA_FRE5>.
    Found 16-bit register for signal <DATA_FRE6>.
    Found 16-bit register for signal <DATA_PHA1>.
    Found 16-bit register for signal <DATA_PHA2>.
    Found 16-bit register for signal <DATA_PHA3>.
    Found 16-bit register for signal <DATA_PHA4>.
    Found 16-bit register for signal <DATA_PHA5>.
    Found 16-bit register for signal <DATA_PHA6>.
    Found 16-bit register for signal <PHA_ACC1>.
    Found 16-bit register for signal <PHA_ACC2>.
    Found 16-bit register for signal <PHA_ACC3>.
    Found 16-bit register for signal <PHA_ACC4>.
    Found 16-bit register for signal <PHA_ACC5>.
    Found 16-bit register for signal <PHA_ACC6>.
    Found 512-bit register for signal <ram_data>.
    Found 16-bit register for signal <trig>.
    Found 16 1-bit 2-to-1 multiplexers.
INFO:Xst:738 - HDL ADVISOR - 512 flip-flops were inferred for signal <ram_data>. You may be trying to describe