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LOG
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Found 16-bit register for signal <PHA_ACC1>. Found 16-bit register for signal <PHA_ACC2>. Found 16-bit register for signal <PHA_ACC3>. Found 16-bit register for signal <PHA_ACC4>. Found 16-bit register for signal <PHA_ACC5>. Found 16-bit register for signal <PHA_ACC6>. Found 512-bit register for signal <ram_data>. Found 16-bit register for signal <trig>. Found 16 1-bit 2-to-1 multiplexers.INFO:Xst:738 - HDL ADVISOR - 512 flip-flops were inferred for signal <ram_data>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. Summary: inferred 688 D-type flip-flop(s). inferred 32 Multiplexer(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 100 1-bit register : 18 16-bit register : 76 2-bit register : 6# Counters : 6 26-bit up counter : 6# Accumulators : 12 16-bit up accumulator : 12# Multiplexers : 2 2-to-1 multiplexer : 1 16-bit 32-to-1 multiplexer : 1# Adders/Subtractors : 24 16-bit adder : 12 1-bit adder : 6 3-bit subtractor : 6# Multipliers : 6 11x3-bit multiplier : 6# Comparators : 12 28-bit comparator greatequal : 6 32-bit comparator greatequal : 6==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.=========================================================================* Low Level Synthesis *=========================================================================Launcher: "rom1.ngo" is up to date.Loading core <rom1> for timing and area information for instance <rom>.WARNING:Xst:1291 - FF/Latch <acc_0> is unconnected in block <DDS1>.WARNING:Xst:1291 - FF/Latch <acc_1> is unconnected in block <DDS1>.WARNING:Xst:1291 - FF/Latch <acc_2> is unconnected in block <DDS1>.WARNING:Xst:1291 - FF/Latch <acc_3> is unconnected in block <DDS1>.WARNING:Xst:1291 - FF/Latch <acc_4> is unconnected in block <DDS1>.WARNING:Xst:1710 - FF/Latch <flag_0> (without init value) is constant in block <DDS1>.WARNING:Xst:1291 - FF/Latch <CONTROL_0> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <CONTROL_1> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <CONTROL_2> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <CONTROL_3> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <CONTROL_0> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <CONTROL_1> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <CONTROL_2> is unconnected in block <top>.WARNING:Xst:1291 - FF/Latch <CONTROL_3> is unconnected in block <top>.Optimizing unit <top> ...Optimizing unit <DDS1> ...Loading device for application Xst from file '3s400.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 32.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4 Number of Slices: 1222 out of 3584 34% Number of Slice Flip Flops: 1554 out of 7168 21% Number of 4 input LUTs: 1112 out of 7168 15% Number of bonded IOBs: 91 out of 141 64% Number of BRAMs: 6 out of 8 75% Number of MULT18X18s: 6 out of 8 75% Number of GCLKs: 4 out of 8 50% Number of DCMs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+NWE_n | BUFGP | 512 |clkin | instance_name_DCM_INST:CLK0| 952 |my_dds4_DDS60_counterclk_outclktemp:Q| NONE | 16 |my_dds4_DDS50_counterclk_outclktemp:Q| NONE | 16 |my_dds4_DDS40_counterclk_outclktemp:Q| NONE | 16 |my_dds4_DDS30_counterclk_outclktemp:Q| NONE | 16 |my_dds4_DDS20_counterclk_outclktemp:Q| NONE | 16 |my_dds4_DDS10_counterclk_outclktemp:Q| NONE | 16 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 10.693ns (Maximum Frequency: 93.519MHz) Minimum input arrival time before clock: 7.159ns Maximum output required time after clock: 14.183ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\毕业设计\fpga程序\sinewave/_ngo -uctop_ucf.ucf -p xc3s400-pq208-4 top.ngc top.ngd Reading NGO file "E:/毕业设计/FPGA程序/sinewave/top.ngc" ...Reading component libraries for design expansion...Launcher: "rom1.ngo" is up to date.Loading design module "e:\毕业设计\fpga程序\sinewave\_ngo\rom1.ngo"...blkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iblkmemsp_v5_0, Coregen 6.1iAnnotating constraints to design from file "top_ucf.ucf" ...Attached a PULLDOWN primitive to pad net SINE5<5> Attached a PULLDOWN primitive to pad net SINE5<6> Attached a PULLDOWN primitive to pad net SINE5<4> Attached a PULLDOWN primitive to pad net SINE5<2> Attached a PULLDOWN primitive to pad net SINE5<3> Attached a PULLDOWN primitive to pad net SINE5<1> Attached a PULLDOWN primitive to pad net SINE6<10> Attached a PULLDOWN primitive to pad net SINE5<0> Attached a PULLDOWN primitive to pad net SINE6<9> Attached a PULLDOWN primitive to pad net SINE6<7> Attached a PULLDOWN primitive to pad net SINE6<8> Attached a PULLDOWN primitive to pad net SINE6<6> Attached a PULLDOWN primitive to pad net SINE6<4> Attached a PULLDOWN primitive to pad net SINE6<5> Attached a PULLDOWN primitive to pad net SINE6<3> Attached a PULLDOWN primitive to pad net SINE6<1> Attached a PULLDOWN primitive to pad net SINE6<2> Attached a PULLDOWN primitive to pad net SINE6<0> Attached a PULLUP primitive to pad net NWE_n Attached a PULLDOWN primitive to pad net rst Attached a PULLUP primitive to pad net NCS0_n Attached a PULLDOWN primitive to pad net DataIN<15> Attached a PULLDOWN primitive to pad net DataIN<14> Attached a PULLDOWN primitive to pad net DataIN<13> Attached a PULLDOWN primitive to pad net DataIN<12> Attached a PULLDOWN primitive to pad net DataIN<11> Attached a PULLDOWN primitive to pad net DataIN<10> Attached a PULLDOWN primitive to pad net DataIN<9> Attached a PULLDOWN primitive to pad net DataIN<8> Attached a PULLDOWN primitive to pad net DataIN<7> Attached a PULLDOWN primitive to pad net DataIN<6> Attached a PULLDOWN primitive to pad net DataIN<5> Attached a PULLDOWN primitive to pad net DataIN<4> Attached a PULLDOWN primitive to pad net DataIN<3> Attached a PULLDOWN primitive to pad net DataIN<2> Attached a PULLDOWN primitive to pad net DataIN<1> Attached a PULLDOWN primitive to pad net DataIN<0> Attached a PULLUP primitive to pad net clk_out Attached a PULLDOWN primitive to pad net SINE1<10> Attached a PULLDOWN primitive to pad net SINE1<9> Attached a PULLDOWN primitive to pad net SINE1<8> Attached a PULLDOWN primitive to pad net SINE1<7> Attached a PULLDOWN primitive to pad net SINE1<6> Attached a PULLDOWN primitive to pad net SINE1<5> Attached a PULLDOWN primitive to pad net SINE1<4> Attached a PULLDOWN primitive to pad net SINE1<3> Attached a PULLDOWN primitive to pad net SINE1<2> Attached a PULLDOWN primitive to pad net SINE1<1> Attached a PULLDOWN primitive to pad net SINE1<0> Attached a PULLDOWN primitive to pad net SINE2<10> Attached a PULLDOWN primitive to pad net SINE2<9> Attached a PULLDOWN primitive to pad net SINE2<8> Attached a PULLDOWN primitive to pad net SINE2<7> Attached a PULLDOWN primitive to pad net SINE2<6> Attached a PULLDOWN primitive to pad net SINE2<5> Attached a PULLDOWN primitive to pad net SINE2<4> Attached a PULLDOWN primitive to pad net SINE2<3> Attached a PULLDOWN primitive to pad net SINE2<2> Attached a PULLDOWN primitive to pad net SINE2<1> Attached a PULLDOWN primitive to pad net SINE2<0> Attached a PULLDOWN primitive to pad net SINE3<10> Attached a PULLDOWN primitive to pad net SINE3<9> Attached a PULLDOWN primitive to pad net SINE3<8> Attached a PULLDOWN primitive to pad net SINE3<7> Attached a PULLDOWN primitive to pad net SINE3<6> Attached a PULLDOWN primitive to pad net SINE3<5> Attached a PULLDOWN primitive to pad net SINE3<4> Attached a PULLDOWN primitive to pad net SINE3<3> Attached a PULLDOWN primitive to pad net SINE3<2> Attached a PULLDOWN primitive to pad net SINE3<1> Attached a PULLDOWN primitive to pad net SINE3<0> Attached a PULLDOWN primitive to pad net SINE4<9> Attached a PULLDOWN primitive to pad net SINE4<8> Attached a PULLDOWN primitive to pad net SINE4<7> Attached a PULLDOWN primitive to pad net SINE4<6> Attached a PULLDOWN primitive to pad net SINE4<5> Attached a PULLDOWN primitive to pad net SINE4<4> Attached a PULLDOWN primitive to pad net SINE4<3> Attached a PULLDOWN primitive to pad net SINE4<2> Attached a PULLDOWN primitive to pad net SINE4<1> Attached a PULLDOWN primitive to pad net SINE4<0> Attached a PULLDOWN primitive to pad net SINE5<10> Attached a PULLDOWN primitive to pad net SINE5<9> Attached a PULLDOWN primitive to pad net SINE5<8> Attached a PULLDOWN primitive to pad net SINE5<7> Checking timing specifications ...Checking expanded design ...WARNING:NgdBuild:477 - clock net 'CLKDV_OUT' has non-clock connections. These problematic connections include: pin I0 on block clk_out1 with type LUT1NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 1Total memory usage is 47248 kilobytesWriting NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "3s400pq208-4".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 67Logic Utilization: Number of Slice Flip Flops: 1,554 out of 7,168 21% Number of 4 input LUTs: 1,030 out of 7,168 14%Logic Distribution: Number of occupied Slices: 1,140 out of 3,584 31% Number of Slices containing only related logic: 1,140 out of 1,140 100% Number of Slices containing unrelated logic: 0 out of 1,140 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 1,120 out of 7,168 15% Number used as logic: 1,030 Number used as a route-thru: 90 Number of bonded IOBs: 92 out of 141 65% Number of Block RAMs: 6 out of 16 37% Number of MULT18X18s: 6 out of 16 37% Number of GCLKs: 3 out of 8 37% Number of DCMs: 1 out of 4 25%Total equivalent gate count for design: 447,247Additional JTAG gate count for IOBs: 4,416Peak Memory Usage: 91 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "top_map.mrp" for details.Completed process "Map".Mapping Module top . . .
MAP command line:
map -intstyle ise -p xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf
Mapping Module top: DONE
Started process "Place & Route".⌨️ 快捷键说明
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