dds4.mrp
来自「Verilog编程」· MRP 代码 · 共 512 行 · 第 1/4 页
MRP
512 行
| PHA_ACC3<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<8> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<9> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<10> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<11> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<12> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<13> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<14> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC3<15> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<0> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<1> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<2> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<4> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<5> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<8> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<9> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<10> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<11> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<12> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<13> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<14> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC4<15> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<0> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<1> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<2> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<4> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<5> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<8> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<9> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<10> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<11> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<12> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<13> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<14> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC5<15> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<0> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<1> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<2> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<4> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<5> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<8> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<9> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<10> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<11> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<12> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<13> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<14> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || PHA_ACC6<15> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || RST | IOB | INPUT | LVCMOS25 | | | | | || SINE1<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE1<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE1<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE1<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE1<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE1<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE1<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE1<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE2<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE3<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE4<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE5<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || SINE6<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.
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