dds4.mrp

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Release 6.1i Map G.23
Xilinx Mapping Report File for Design 'dds4'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o dds4_map.ncd dds4.ngd dds4.pcf 
Target Device  : x3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.16 $
Mapped Date    : Wed May 23 20:57:11 2007

Design Summary
--------------
Number of errors:      1
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         402 out of   7,168    5%
  Number of 4 input LUTs:             709 out of   7,168    9%
Logic Distribution:
  Number of occupied Slices:                          410 out of   3,584   11%
    Number of Slices containing only related logic:     410 out of     410  100%
    Number of Slices containing unrelated logic:          0 out of     410    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            799 out of   7,168   11%
  Number used as logic:                709
  Number used as a route-thru:          90
  Number of bonded IOBs:             350 out of     141  248% (OVERMAPPED)
    IOB Flip Flops:                   300
  Number of Block RAMs:                6 out of      16   37%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  406,725
Additional JTAG gate count for IOBs:  16,800
Peak Memory Usage:  84 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report

Section 1 - Errors
------------------
ERROR:Pack:18 - The design is too large for the given device and package. 
   Please check the Design Summary section to see which resource requirement for
   your design exceeds the resources available in the device.
   

If the slice count exceeds device resources you might try to disable
   register ordering (-r).  Also if your design contains AREA_GROUPs, you may be
   able to improve density by adding COMPRESSION to your AREA_GROUPs if you
   haven't done so already.
   

NOTE: An NCD file will still be generated to allow you to examine the mapped
   design.  This file is intended for evaluation use only, and will not process
   successfully through PAR.
   

This mapped NCD file can be used to evaluate how the design's logic has been
   mapped into FPGA logic resources.  It can also be used to analyze
   preliminary, logic-level (pre-route) timing with one of the Xilinx static
   timing analysis tools (TRCE or Timing Analyzer).

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "CLK0_BUFGP" (output signal=CLK0_BUFGP)

Section 4 - Removed Logic Summary
---------------------------------
   6 block(s) removed
   8 block(s) optimized away

Section 5 - Removed Logic
-------------------------
Unused block "DDS10_rom/VCC" (ONE) removed.
Unused block "DDS20_rom/VCC" (ONE) removed.
Unused block "DDS30_rom/VCC" (ONE) removed.
Unused block "DDS40_rom/VCC" (ONE) removed.
Unused block "DDS50_rom/VCC" (ONE) removed.
Unused block "DDS60_rom/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		DDS10_rom/GND
GND 		DDS20_rom/GND
GND 		DDS30_rom/GND
GND 		DDS40_rom/GND
GND 		DDS50_rom/GND
GND 		DDS60_rom/GND