fifo_asyn.coregen_log

来自「Verilog编程」· COREGEN_LOG 代码 · 共 63 行

# Xilinx CORE Generator 6.1.03i
# User = 丁伟森
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\ise6.1\tst\coregen.log
# lockprojectprops=false
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\ise6.1\tst
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=Verilog VHDL
# xilinxfamily=Spartan3
# outputoption=OutputProducts
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\ise6.1\tst
SETPROJECT e:\ise6.1\tst
Set current Project to E:\ise6.1\tst
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET FlowVendor = Foundation_iSE
SET CloseIPGUIAfterGeneration=true
SET OutputOption = OutputProducts
SET OutputProducts = ImpNetlist;ASYSymbol;VHDLSim;VerilogSim
SET SimulationOutputProducts = Verilog VHDL
SET LockProjectProps = false
SETXIPCPORTHOST 1473
XIPCPJLAUNCHCOREGUI Asynchronous_FIFO Xilinx,_Inc. 5.1
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = true
CSET almost_empty_flag = true
CSET memory_type = block
CSET read_error = false
CSET fifo_depth = 255
CSET input_data_width = 16
CSET write_count = false
CSET Component_Name = fifo_asyn
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 2
GENERATE
Preparing to elaborate core...
Elaborating the module...
Generating the core .EDN implementation netlist...
Generating the .VHO/.VHD simulation support files...
Generating the .VEO/.V simulation support files...
Generating the .ASY symbol file...
Generating ISE symbol file...
# Executing: C:\Xilinx\bin\nt\asy2sym.exe E:\ise6.1\tst\fifo_asyn.asy
# Release 6.1i - asy2sym G.26
# Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
# Execution Complete.  Return code: 0
Successfully generated <fifo_asyn> (Asynchronous FIFO 5.1)