dds1.syr

Verilog编程

#      16-bit adder                : 4
# Multipliers                      : 1
#      11x3-bit multiplier         : 1
# Comparators                      : 2
#      28-bit comparator greatequal: 1
#      32-bit comparator greatequal: 1

Cell Usage :
# BELS                             : 342
#      GND                         : 2
#      LUT1                        : 17
#      LUT1_L                      : 13
#      LUT2                        : 48
#      LUT2_L                      : 43
#      LUT3                        : 1
#      LUT3_L                      : 1
#      LUT4                        : 5
#      LUT4_L                      : 5
#      MUXCY                       : 124
#      VCC                         : 1
#      XORCY                       : 82
# FlipFlops/Latches                : 119
#      FDC                         : 45
#      FDCE                        : 48
#      FDCPE                       : 26
# RAMS                             : 1
#      RAMB16_S18                  : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 62
#      IBUF                        : 51
#      OBUF                        : 11
# MULTs                            : 1
#      MULT18X18                   : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     102  out of   3584     2%  
 Number of Slice Flip Flops:           119  out of   7168     1%  
 Number of 4 input LUTs:               133  out of   7168     1%  
 Number of bonded IOBs:                 62  out of    141    43%  
 Number of BRAMs:                        1  out of     16     6%  
 Number of MULT18X18s:                   1  out of     16     6%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 104   |
counterclk_outclktemp:Q            | NONE                   | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.693ns (Maximum Frequency: 93.519MHz)
   Minimum input arrival time before clock: 4.306ns
   Maximum output required time after clock: 14.183ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               10.693ns (Levels of Logic = 47)
  Source:            counterclk_cout_0 (FF)
  Destination:       counterclk_cout_25 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: counterclk_cout_0 to counterclk_cout_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            3   0.619   0.577  counterclk_cout_0 (counterclk_cout_0)
     LUT4_L:I0->LO         1   0.720   0.000  counterclk_Mcompar__n0002_inst_lut4_61 (counterclk_Mcompar__n0002_inst_lut4_6)
     MUXCY:S->O            1   0.629   0.000  counterclk_Mcompar__n0002_inst_cy_35 (counterclk_Mcompar__n0002_inst_cy_35)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_36 (counterclk_Mcompar__n0002_inst_cy_36)
     MUXCY:CI->O           1   0.091   0.000  counterclk_Mcompar__n0002_inst_cy_37 (counterclk_Mcompar__n0002_inst_cy_37)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_38 (counterclk_Mcompar__n0002_inst_cy_38)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_39 (counterclk_Mcompar__n0002_inst_cy_39)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_40 (counterclk_Mcompar__n0002_inst_cy_40)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_41 (counterclk_Mcompar__n0002_inst_cy_41)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_42 (counterclk_Mcompar__n0002_inst_cy_42)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_43 (counterclk_Mcompar__n0002_inst_cy_43)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_44 (counterclk_Mcompar__n0002_inst_cy_44)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_45 (counterclk_Mcompar__n0002_inst_cy_45)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_46 (counterclk_Mcompar__n0002_inst_cy_46)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_47 (counterclk_Mcompar__n0002_inst_cy_47)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_48 (counterclk_Mcompar__n0002_inst_cy_48)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_49 (counterclk_Mcompar__n0002_inst_cy_49)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_50 (counterclk_Mcompar__n0002_inst_cy_50)
     MUXCY:CI->O           1   0.090   0.000  counterclk_Mcompar__n0002_inst_cy_51 (counterclk_Mcompar__n0002_inst_cy_51)
     MUXCY:CI->O          28   0.331   1.317  counterclk_Mcompar__n0002_inst_cy_52 (counterclk_Mcompar__n0002_inst_cy_52)
     LUT1_L:I0->LO         1   0.720   0.000  counterclk__n0002_rt (counterclk__n0002_rt)
     MUXCY:S->O            1   0.629   0.000  counterclk_cout_inst_cy_55 (counterclk_cout_inst_cy_55)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_56 (counterclk_cout_inst_cy_56)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_57 (counterclk_cout_inst_cy_57)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_58 (counterclk_cout_inst_cy_58)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_59 (counterclk_cout_inst_cy_59)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_60 (counterclk_cout_inst_cy_60)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_61 (counterclk_cout_inst_cy_61)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_62 (counterclk_cout_inst_cy_62)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_63 (counterclk_cout_inst_cy_63)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_64 (counterclk_cout_inst_cy_64)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_65 (counterclk_cout_inst_cy_65)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_66 (counterclk_cout_inst_cy_66)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_67 (counterclk_cout_inst_cy_67)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_68 (counterclk_cout_inst_cy_68)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_69 (counterclk_cout_inst_cy_69)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_70 (counterclk_cout_inst_cy_70)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_71 (counterclk_cout_inst_cy_71)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_72 (counterclk_cout_inst_cy_72)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_73 (counterclk_cout_inst_cy_73)
     MUXCY:CI->O           1   0.091   0.000  counterclk_cout_inst_cy_74 (counterclk_cout_inst_cy_74)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_75 (counterclk_cout_inst_cy_75)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_76 (counterclk_cout_inst_cy_76)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_77 (counterclk_cout_inst_cy_77)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_78 (counterclk_cout_inst_cy_78)
     MUXCY:CI->O           1   0.090   0.000  counterclk_cout_inst_cy_79 (counterclk_cout_inst_cy_79)
     MUXCY:CI->O           0   0.090   0.000  counterclk_cout_inst_cy_80 (counterclk_cout_inst_cy_80)
     XORCY:CI->O           1   0.939   0.000  counterclk_cout_inst_sum_41 (counterclk_cout_inst_sum_41)
     FDCPE:D                   0.502          counterclk_cout_25
    ----------------------------------------
    Total                     10.693ns (8.799ns logic, 1.894ns route)
                                       (82.3% logic, 17.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counterclk_outclktemp:Q'
Delay:               5.253ns (Levels of Logic = 17)
  Source:            PHA_ACC_t1_0 (FF)
  Destination:       PHA_ACC_t1_15 (FF)
  Source Clock:      counterclk_outclktemp:Q rising
  Destination Clock: counterclk_outclktemp:Q rising

  Data Path: PHA_ACC_t1_0 to PHA_ACC_t1_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.619   0.577  PHA_ACC_t1_0 (PHA_ACC_t1_0)
     LUT2:I1->O            2   0.720   0.000  PHA_ACC_t1_Madd__n0000_inst_lut2_01 (PHA_ACC_t1_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.629   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_0 (PHA_ACC_t1_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_1 (PHA_ACC_t1_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_2 (PHA_ACC_t1_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_3 (PHA_ACC_t1_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_4 (PHA_ACC_t1_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_5 (PHA_ACC_t1_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_6 (PHA_ACC_t1_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_7 (PHA_ACC_t1_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_8 (PHA_ACC_t1_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_9 (PHA_ACC_t1_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_10 (PHA_ACC_t1_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_11 (PHA_ACC_t1_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_12 (PHA_ACC_t1_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_13 (PHA_ACC_t1_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  PHA_ACC_t1_Madd__n0000_inst_cy_14 (PHA_ACC_t1_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  PHA_ACC_t1_Madd__n0000_inst_sum_15 (PHA_ACC_t1__n0000<15>)
     FDC:D                     0.502          PHA_ACC_t1_15
    ----------------------------------------
    Total                      5.253ns (4.676ns logic, 0.577ns route)
                                       (89.0% logic, 11.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              4.306ns (Levels of Logic = 3)
  Source:            SCLR (PAD)
  Destination:       rom/B5 (RAM)
  Destination Clock: CLK rising

  Data Path: SCLR to rom/B5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.492   0.240  SCLR_IBUF (SCLR_IBUF)
     LUT1:I0->O            1   0.720   0.240  _n00121 (_n0012)
     begin scope: 'rom'
     RAMB16_S18:EN             1.614          B5
    ----------------------------------------
    Total                      4.306ns (3.826ns logic, 0.480ns route)
                                       (88.9% logic, 11.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              14.183ns (Levels of Logic = 4)
  Source:            rom/B5 (RAM)
  Destination:       SINE<10> (PAD)
  Source Clock:      CLK rising

  Data Path: rom/B5 to SINE<10>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S18:CLK->DO0    1   3.509   0.240  B5 (dout<0>)
     end scope: 'rom'
     MULT18X18:A0->P10     1   3.822   0.240  Mmult__n0009_inst_mult_0 (_n0009<10>)
     LUT1:I0->O            1   0.720   0.240  Madd__n0005_Result1 (SINE_10_OBUF)
     OBUF:I->O                 5.412          SINE_10_OBUF (SINE<10>)
    ----------------------------------------
    Total                     14.183ns (13.463ns logic, 0.720ns route)
                                       (94.9% logic, 5.1% route)

=========================================================================
CPU : 18.87 / 20.65 s | Elapsed : 19.00 / 21.00 s
 
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Total memory usage is 79064 kilobytes