top.twr

来自「Verilog编程」· TWR 代码 · 共 164 行

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Release 6.1i Trace G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml top top.ncd -o top.twr
top.pcf


Design file:              top.ncd
Physical constraint file: top.pcf
Device,speed:             xc3s400,-4 (PREVIEW 1.27 2003-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock NWE_n
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
DataIN<0>   |    4.238(F)|    1.114(F)|NWE_n_BUFGP       |   0.000|
DataIN<10>  |    4.634(F)|    0.360(F)|NWE_n_BUFGP       |   0.000|
DataIN<11>  |    4.711(F)|    0.288(F)|NWE_n_BUFGP       |   0.000|
DataIN<12>  |    4.310(F)|    0.424(F)|NWE_n_BUFGP       |   0.000|
DataIN<13>  |    5.526(F)|    0.383(F)|NWE_n_BUFGP       |   0.000|
DataIN<14>  |    4.652(F)|    0.080(F)|NWE_n_BUFGP       |   0.000|
DataIN<15>  |    4.286(F)|    0.358(F)|NWE_n_BUFGP       |   0.000|
DataIN<1>   |    4.612(F)|    0.818(F)|NWE_n_BUFGP       |   0.000|
DataIN<2>   |    3.640(F)|    1.141(F)|NWE_n_BUFGP       |   0.000|
DataIN<3>   |    4.002(F)|    1.094(F)|NWE_n_BUFGP       |   0.000|
DataIN<4>   |    4.470(F)|    0.587(F)|NWE_n_BUFGP       |   0.000|
DataIN<5>   |    4.326(F)|    0.382(F)|NWE_n_BUFGP       |   0.000|
DataIN<6>   |    5.357(F)|   -0.225(F)|NWE_n_BUFGP       |   0.000|
DataIN<7>   |    5.472(F)|    0.531(F)|NWE_n_BUFGP       |   0.000|
DataIN<8>   |    4.922(F)|    0.949(F)|NWE_n_BUFGP       |   0.000|
DataIN<9>   |    4.118(F)|    1.027(F)|NWE_n_BUFGP       |   0.000|
NCS0_n      |    6.076(F)|    0.938(F)|NWE_n_BUFGP       |   0.000|
addr<0>     |   11.899(F)|    0.549(F)|NWE_n_BUFGP       |   0.000|
addr<1>     |   11.640(F)|    0.023(F)|NWE_n_BUFGP       |   0.000|
addr<2>     |   11.505(F)|    0.294(F)|NWE_n_BUFGP       |   0.000|
addr<3>     |   11.205(F)|   -0.869(F)|NWE_n_BUFGP       |   0.000|
addr<4>     |   11.526(F)|   -0.687(F)|NWE_n_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clkin to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
SINE1<0>    |   15.653(R)|CLKDV_OUT         |   0.000|
SINE1<10>   |   17.180(R)|CLKDV_OUT         |   0.000|
SINE1<1>    |   15.925(R)|CLKDV_OUT         |   0.000|
SINE1<2>    |   16.215(R)|CLKDV_OUT         |   0.000|
SINE1<3>    |   16.842(R)|CLKDV_OUT         |   0.000|
SINE1<4>    |   18.434(R)|CLKDV_OUT         |   0.000|
SINE1<5>    |   17.333(R)|CLKDV_OUT         |   0.000|
SINE1<6>    |   17.933(R)|CLKDV_OUT         |   0.000|
SINE1<7>    |   16.652(R)|CLKDV_OUT         |   0.000|
SINE1<8>    |   16.739(R)|CLKDV_OUT         |   0.000|
SINE1<9>    |   17.149(R)|CLKDV_OUT         |   0.000|
SINE2<0>    |   15.601(R)|CLKDV_OUT         |   0.000|
SINE2<10>   |   17.091(R)|CLKDV_OUT         |   0.000|
SINE2<1>    |   16.749(R)|CLKDV_OUT         |   0.000|
SINE2<2>    |   16.664(R)|CLKDV_OUT         |   0.000|
SINE2<3>    |   16.794(R)|CLKDV_OUT         |   0.000|
SINE2<4>    |   16.810(R)|CLKDV_OUT         |   0.000|
SINE2<5>    |   16.593(R)|CLKDV_OUT         |   0.000|
SINE2<6>    |   17.029(R)|CLKDV_OUT         |   0.000|
SINE2<7>    |   16.967(R)|CLKDV_OUT         |   0.000|
SINE2<8>    |   16.530(R)|CLKDV_OUT         |   0.000|
SINE2<9>    |   17.196(R)|CLKDV_OUT         |   0.000|
SINE3<0>    |   14.118(R)|CLKDV_OUT         |   0.000|
SINE3<10>   |   16.989(R)|CLKDV_OUT         |   0.000|
SINE3<1>    |   15.250(R)|CLKDV_OUT         |   0.000|
SINE3<2>    |   15.886(R)|CLKDV_OUT         |   0.000|
SINE3<3>    |   15.891(R)|CLKDV_OUT         |   0.000|
SINE3<4>    |   16.696(R)|CLKDV_OUT         |   0.000|
SINE3<5>    |   15.896(R)|CLKDV_OUT         |   0.000|
SINE3<6>    |   15.361(R)|CLKDV_OUT         |   0.000|
SINE3<7>    |   15.550(R)|CLKDV_OUT         |   0.000|
SINE3<8>    |   15.694(R)|CLKDV_OUT         |   0.000|
SINE3<9>    |   16.009(R)|CLKDV_OUT         |   0.000|
SINE4<0>    |   14.735(R)|CLKDV_OUT         |   0.000|
SINE4<10>   |   17.946(R)|CLKDV_OUT         |   0.000|
SINE4<1>    |   15.397(R)|CLKDV_OUT         |   0.000|
SINE4<2>    |   15.048(R)|CLKDV_OUT         |   0.000|
SINE4<3>    |   17.077(R)|CLKDV_OUT         |   0.000|
SINE4<4>    |   16.960(R)|CLKDV_OUT         |   0.000|
SINE4<5>    |   16.929(R)|CLKDV_OUT         |   0.000|
SINE4<6>    |   17.212(R)|CLKDV_OUT         |   0.000|
SINE4<7>    |   17.614(R)|CLKDV_OUT         |   0.000|
SINE4<8>    |   18.175(R)|CLKDV_OUT         |   0.000|
SINE4<9>    |   19.160(R)|CLKDV_OUT         |   0.000|
SINE5<0>    |   15.895(R)|CLKDV_OUT         |   0.000|
SINE5<10>   |   18.077(R)|CLKDV_OUT         |   0.000|
SINE5<1>    |   16.071(R)|CLKDV_OUT         |   0.000|
SINE5<2>    |   15.128(R)|CLKDV_OUT         |   0.000|
SINE5<3>    |   16.752(R)|CLKDV_OUT         |   0.000|
SINE5<4>    |   15.788(R)|CLKDV_OUT         |   0.000|
SINE5<5>    |   16.153(R)|CLKDV_OUT         |   0.000|
SINE5<6>    |   16.343(R)|CLKDV_OUT         |   0.000|
SINE5<7>    |   18.815(R)|CLKDV_OUT         |   0.000|
SINE5<8>    |   18.716(R)|CLKDV_OUT         |   0.000|
SINE5<9>    |   18.247(R)|CLKDV_OUT         |   0.000|
SINE6<0>    |   15.507(R)|CLKDV_OUT         |   0.000|
SINE6<10>   |   17.030(R)|CLKDV_OUT         |   0.000|
SINE6<1>    |   15.422(R)|CLKDV_OUT         |   0.000|
SINE6<2>    |   15.801(R)|CLKDV_OUT         |   0.000|
SINE6<3>    |   16.529(R)|CLKDV_OUT         |   0.000|
SINE6<4>    |   16.416(R)|CLKDV_OUT         |   0.000|
SINE6<5>    |   15.913(R)|CLKDV_OUT         |   0.000|
SINE6<6>    |   16.627(R)|CLKDV_OUT         |   0.000|
SINE6<7>    |   16.775(R)|CLKDV_OUT         |   0.000|
SINE6<8>    |   16.855(R)|CLKDV_OUT         |   0.000|
SINE6<9>    |   16.554(R)|CLKDV_OUT         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock NWE_n
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
NWE_n          |         |         |         |   12.926|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock clkin
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
NWE_n          |         |    6.523|         |         |
clkin          |   11.938|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
clkin          |clk_out1       |    9.518|
clkin          |clk_out2       |   10.563|
clkin          |clk_out3       |    9.545|
clkin          |clk_out4       |   10.576|
clkin          |clk_out5       |    7.970|
clkin          |clk_out6       |    7.447|
---------------+---------------+---------+

Analysis completed Thu May 08 16:24:45 2008
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Peak Memory Usage: 74 MB