my_dcm1.v

来自「Verilog编程」· Verilog 代码 · 共 99 行

// Module my_dcm1
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST

module my_dcm1(
      LOCKED_OUT,
      CLKIN_IN,
      CLK180_OUT,
      CLKFX_OUT,
      CLK0_OUT,
      CLKIN_IBUFG_OUT);

input CLKIN_IN;

output LOCKED_OUT;
output CLK180_OUT;
output CLKFX_OUT;
output CLK0_OUT;
output CLKIN_IBUFG_OUT;

wire CLKIN_IBUFG;
wire CLKFB_IN;
wire CLK0_BUF;
wire CLK180_BUF;
wire CLKFX_BUF;

assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;

DCM DCM_INST(
    .CLKIN (CLKIN_IBUFG),
    .CLKFB (CLKFB_IN),
    .RST (1'b0),
    .PSEN (1'b0),
    .PSINCDEC (1'b0),
    .PSCLK (1'b0),
    .DSSEN (1'b0),
    .CLK0 (CLK0_BUF),
    .CLK90 (),
    .CLK180 (CLK180_BUF),
    .CLK270 (),
    .CLKDV (),
    .CLK2X (),
    .CLK2X180 (),
    .CLKFX (CLKFX_BUF),
    .CLKFX180 (),
    .STATUS (),
    .LOCKED (LOCKED_OUT),
    .PSDONE ());
// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
// synthesis attribute CLKDV_DIVIDE of DCM_INST is 2
// synthesis attribute CLKFX_DIVIDE of DCM_INST is 2
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is 2
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
// synthesis attribute CLKIN_PERIOD of DCM_INST is 20
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
// synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
// synthesis attribute PHASE_SHIFT of DCM_INST is 0
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
// Period Jitter (unit interval) = 0.04 UI
// Period Jitter (Peak-to-Peak) = 0.79 ns
// synthesis translate_off
 defparam DCM_INST.CLK_FEEDBACK="1X";
 defparam DCM_INST.CLKDV_DIVIDE=2;
 defparam DCM_INST.CLKFX_DIVIDE=2;
 defparam DCM_INST.CLKFX_MULTIPLY=2;
 defparam DCM_INST.CLKIN_DIVIDE_BY_2="FALSE";
 defparam DCM_INST.CLKIN_PERIOD=20;
 defparam DCM_INST.CLKOUT_PHASE_SHIFT="NONE";
 defparam DCM_INST.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
 defparam DCM_INST.DFS_FREQUENCY_MODE="LOW";
 defparam DCM_INST.DLL_FREQUENCY_MODE="LOW";
 defparam DCM_INST.DUTY_CYCLE_CORRECTION="TRUE";
 defparam DCM_INST.PHASE_SHIFT=0;
 defparam DCM_INST.STARTUP_WAIT="FALSE";
// synthesis translate_on

IBUFG CLKIN_IBUFG_INST(
    .I (CLKIN_IN),
    .O (CLKIN_IBUFG));

BUFG CLK0_BUFG_INST(
    .I (CLK0_BUF),
    .O (CLKFB_IN));

BUFG CLK180_BUFG_INST(
    .I (CLK180_BUF),
    .O (CLK180_OUT));

BUFG CLKFX_BUFG_INST(
    .I (CLKFX_BUF),
    .O (CLKFX_OUT));

endmodule