tst.syr

Verilog编程

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: tst.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : tst.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : tst
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : tst
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : ONLY
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : tst.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:Xst:878 - rom.v line 96: Unrecognized directive. Ignoring.
Compiling source file "rom.v"
Module <rom> compiled
Compiling source file "tst.v"
Module <tst> compiled
No errors in compilation
Analysis of file <tst.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <tst>.
WARNING:Xst:863 - tst.v line 17: Name conflict (<q> and <Q>, renaming q as q_rnm0).
Module <tst> is correct for synthesis.
 
Analyzing module <rom>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <tst>.
    Related source file is tst.v.
WARNING:Xst:646 - Signal <q_rnm0<13:0>> is assigned but never used.
    Found 28-bit register for signal <PINC>.
    Found 28-bit register for signal <POFF>.
    Found 28-bit adder for signal <q_rnm0>.
    Found 28-bit up accumulator for signal <sum>.
    Summary:
	inferred   1 Accumulator(s).
	inferred  56 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <tst> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
  28-bit register                  : 2
# Accumulators                     : 1
  28-bit up accumulator            : 1
# Adders/Subtractors               : 1
  28-bit adder                     : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "rom.edn" "rom.ngo"
INFO:NgdBuild - Release 6.1i - edif2ngd G.23
INFO:NgdBuild - Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Writing the design to "rom.ngo"...
Loading core <rom> for timing and area information for instance <sin>.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : tst.ngr
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 46

Cell Usage :
# BELS                             : 74
#      GND                         : 1
#      LUT3                        : 1
#      LUT4                        : 44
#      MUXF5                       : 18
#      MUXF6                       : 9
#      VCC                         : 1
# FlipFlops/Latches                : 87
#      FDC                         : 28
#      FDCE                        : 56
#      FDE                         : 3
# RAMS                             : 13
#      RAMB16_S1                   : 5
#      RAMB16_S9                   : 8
=========================================================================
CPU : 10.44 / 11.36 s | Elapsed : 10.00 / 11.00 s
 
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Total memory usage is 54888 kilobytes