tst.gfl

Verilog编程

top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Generate PROM, ACE, or JTAG File
top.ace
xilinx.sys
top.mpm
top.mcs
top.prm
top.dst
top.exo
top.tek
top.hex
top.svf
top.stapl
impact.cmd
_impact.log
_impact.cmd
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
DDS1.ngc
top.ngc
DDS1.ngr
dds4.ngr
top.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\ise6.1\tst/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top_ucf.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Generate PROM, ACE, or JTAG File
top.ace
xilinx.sys
top.mpm
top.mcs
top.prm
top.dst
top.exo
top.tek
top.hex
top.svf
top.stapl
impact.cmd
_impact.log
_impact.cmd
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\ise6.1\tst/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top_ucf.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Generate PROM, ACE, or JTAG File
top.ace
xilinx.sys
top.mpm
top.mcs
top.prm
top.dst
top.exo
top.tek
top.hex
top.svf
top.stapl
impact.cmd
_impact.log
_impact.cmd
# ModelSim : Simulate Behavioral Verilog Model
ding_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
ding_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
arm.vhw
arm.ano
arm.tfw
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
arm.vhw
arm.ano
arm.tfw
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
armtst.lso
# xst flow : RunXST
armtst.syr
armtst.prj
armtst.sprj
armtst.ana
armtst.stx
armtst.cmd_log
armtst.ngc
armtst.ngr
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
armtst.syr
armtst.prj
armtst.sprj
armtst.ana
armtst.stx
armtst.cmd_log
armtst.ngc
armtst.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\ise6.1\tst/_ngo
armtst.ngd
armtst_ngdbuild.nav
armtst.bld
armtst_ucf.ucf.untf
armtst.cmd_log
# Implementation : Generate Post-Translate Simulation Model
armtst_translate.v
armtst_translate.v
armtst_translate.nlf
armtst.xlate_nlf
armtst.versim_xlate
armtst.cmd_log
# Simulation :Simulate Post-Translate Verilog Model
arm.translate_tfw
_remap.tmp
__projnav/temp.rsp
# ModelSim : Simulate Post-Translate VHDL Model
arm.ndo
# ModelSim : Simulate Post-Translate Verilog Model
vsim.wlf
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
arm.vhw
arm.ano
arm.tfw
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Simulation :Simulate Post-Translate Verilog Model
arm.translate_tfw
_remap.tmp
__projnav/temp.rsp
# ModelSim : Simulate Post-Translate VHDL Model
arm.ndo
# ModelSim : Simulate Post-Translate Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
arm.vhw
arm.ano
arm.tfw
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngc
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngc
tst.ngr
# View RTL Schematic
tst.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngc
tst.ngr
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
a1.lso
# xst flow : RunXST
a1.syr
a1.prj
a1.sprj
a1.ana
a1.stx
a1.cmd_log
# XST (Creating Lso File) : 
a1.lso
# xst flow : RunXST
a1.syr
a1.prj
a1.sprj
a1.ana
a1.stx
a1.cmd_log
# XST (Creating Lso File) : 
a1.lso
# xst flow : RunXST
a1.syr
a1.prj
a1.sprj
a1.ana
a1.stx
a1.cmd_log
a1.ngr
# View RTL Schematic
a1.ngr
# View RTL Schematic
tst.ngr
# View RTL Schematic
tst.ngr
# View RTL Schematic
a1.ngr
# Schematic : PDCL (jhdparse)
__projnav/aa_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/aa_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/aa_jhdparse_tcl.rsp
# Schematic : View Verilog Functional Model
aa.vf
# XST (Creating Lso File) : 
aa.lso
# xst flow : RunXST
aa.syr
aa.prj
aa.sprj
aa.ana
aa.stx
aa.cmd_log
# Verilog : Create Schematic Symbol
a1.spl
__projnav/jhdparse.log
# View RTL Schematic
a1.ngr
# XST (Creating Lso File) : 
a1.lso
# xst flow : RunXST
a1.syr
a1.prj
a1.sprj
a1.ana
a1.stx
a1.cmd_log
a1.ngr
# XST (Creating Lso File) : 
a1.lso
# xst flow : RunXST
a1.syr
a1.prj
a1.sprj
a1.ana
a1.stx
a1.cmd_log
a1.ngr
# View RTL Schematic
a1.ngr
# XST (Creating Lso File) : 
b.lso
# xst flow : RunXST
b.syr
b.prj
b.sprj
b.ana
b.stx
b.cmd_log
b.ngr
# View RTL Schematic
b.ngr
# Verilog : Create Schematic Symbol
b.spl
__projnav/jhdparse.log
# Verilog : Create Schematic Symbol
a1.spl
__projnav/jhdparse.log
# Verilog : Create Schematic Symbol
a1.spl
__projnav/jhdparse.log
# View RTL Schematic
a1.ngr
# XST (Creating Lso File) : 
a1.lso
# xst flow : RunXST
a1.syr
a1.prj
a1.sprj
a1.ana
a1.stx
a1.cmd_log
a1.ngr
# View RTL Schematic
a1.ngr
# Verilog : Create Schematic Symbol
tst.spl
__projnav/jhdparse.log
# View RTL Schematic
tst.ngr
# View RTL Schematic
tst.ngr
# View RTL Schematic
tst.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
arm.vhw
arm.ano
arm.tfw
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
ding_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
ding_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ProjNav -> New Source -> TBW
E:\ise6.1\tst\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ding_tbw.vhw
ding_tbw.ano
ding_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
ding_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ding_tbw.vhw
ding_tbw.ano
ding_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
ding_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
TST1.lso
# xst flow : RunXST
TST1.syr
TST1.prj
TST1.sprj
TST1.ana
TST1.stx
TST1.cmd_log
TST1.ngc
TST1.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\fpga_program\ise6.1\tst/_ngo
TST1.ngd
TST1_ngdbuild.nav
TST1.bld
tst1_ucf.ucf.untf
TST1.cmd_log
# Implementation : Map
TST1_map.ncd
TST1.ngm
TST1.pcf
TST1.nc1
TST1.mrp
TST1_map.mrp
TST1.mdf
__projnav/map.log
TST1.cmd_log
MAP_NO_GUIDE_FILE_CPF "TST1"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
TST1.twr
TST1.twx
TST1.tsi
TST1.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
TST1.ncd
TST1.par
TST1.pad
TST1_pad.txt
TST1_pad.csv
TST1.pad_txt
TST1.dly
reportgen.log
TST1.xpi
TST1.grf
TST1.itr
TST1_last_par.ncd
__projnav/par.log
TST1.placed_ncd_tracker
TST1.routed_ncd_tracker
TST1.cmd_log
PAR_NO_GUIDE_FILE_CPF "TST1"
# Generate Programming File
__projnav/TST1_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
TST1.ut
# Generate Programming File
TST1.bgn
TST1.rbt
TST1.ll
TST1.msk
TST1.drc
TST1.nky
TST1.bit
TST1.bin
TST1.isc
TST1.cmd_log
# Configure Device (iMPACT)
TST1.prm
TST1.isc
TST1.svf
xilinx.sys
TST1.mcs
TST1.exo
TST1.hex
TST1.tek
TST1.dst
TST1.dst_compressed
TST1.mpm
_impact.cmd
_impact.log
# XST (Creating Lso File) : 
TST11.lso
# xst flow : RunXST
TST11.syr
TST11.prj
TST11.sprj
TST11.ana
TST11.stx
TST11.cmd_log
TST11.ngc
TST11.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\fpga_program\ise6.1\tst/_ngo
TST11.ngd
TST11_ngdbuild.nav
TST11.bld
.untf
TST11.cmd_log
# Implementation : Map
TST11_map.ncd
TST11.ngm
TST11.pcf
TST11.nc1
TST11.mrp
TST11_map.mrp
TST11.mdf
__projnav/map.log
TST11.cmd_log
MAP_NO_GUIDE_FILE_CPF "TST11"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
TST11.twr
TST11.twx
TST11.tsi
TST11.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
TST11.ncd
TST11.par
TST11.pad
TST11_pad.txt
TST11_pad.csv
TST11.pad_txt
TST11.dly
reportgen.log
TST11.xpi
TST11.grf
TST11.itr
TST11_last_par.ncd
__projnav/par.log
TST11.placed_ncd_tracker
TST11.routed_ncd_tracker
TST11.cmd_log
PAR_NO_GUIDE_FILE_CPF "TST11"
# Generate Programming File
__projnav/TST11_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
TST11.ut
# Generate Programming File
TST11.bgn
TST11.rbt
TST11.ll
TST11.msk
TST11.drc
TST11.nky
TST11.bit
TST11.bin
TST11.isc
TST11.cmd_log
# Configure Device (iMPACT)
TST11.prm
TST11.isc
TST11.svf
xilinx.sys
TST11.mcs
TST11.exo
TST11.hex
TST11.tek
TST11.dst
TST11.dst_compressed
TST11.mpm
_impact.cmd
_impact.log
# xst flow : RunXST