top.par

Verilog编程

Release 6.1i Par G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

ICBCOA-DD4742DF::  Thu May 08 16:23:47 2008


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd
top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.27 2003-11-04.


Resolved that IOB <SINE2<10>> must be placed at site P205.
Resolved that IOB <DataIN<0>> must be placed at site P37.
Resolved that IOB <DataIN<1>> must be placed at site P36.
Resolved that IOB <DataIN<2>> must be placed at site P35.
Resolved that IOB <clkin> must be placed at site P79.
Resolved that IOB <DataIN<3>> must be placed at site P34.
Resolved that IOB <DataIN<4>> must be placed at site P33.
Resolved that IOB <DataIN<5>> must be placed at site P31.
Resolved that IOB <DataIN<6>> must be placed at site P29.
Resolved that IOB <DataIN<7>> must be placed at site P28.
Resolved that IOB <DataIN<8>> must be placed at site P27.
Resolved that IOB <DataIN<9>> must be placed at site P26.
Resolved that IOB <addr<0>> must be placed at site P64.
Resolved that IOB <addr<1>> must be placed at site P58.
Resolved that IOB <addr<2>> must be placed at site P57.
Resolved that IOB <addr<3>> must be placed at site P52.
Resolved that IOB <addr<4>> must be placed at site P51.
Resolved that IOB <DataIN<10>> must be placed at site P24.
Resolved that IOB <DataIN<11>> must be placed at site P22.
Resolved that IOB <DataIN<12>> must be placed at site P21.
Resolved that IOB <DataIN<13>> must be placed at site P20.
Resolved that IOB <DataIN<14>> must be placed at site P19.
Resolved that IOB <DataIN<15>> must be placed at site P18.
Resolved that IOB <NWE_n> must be placed at site P63.
Resolved that IOB <SINE2<0>> must be placed at site P190.
Resolved that IOB <SINE2<1>> must be placed at site P191.
Resolved that IOB <SINE2<2>> must be placed at site P194.
Resolved that IOB <SINE2<3>> must be placed at site P196.
Resolved that IOB <SINE2<4>> must be placed at site P197.
Resolved that IOB <SINE2<5>> must be placed at site P198.
Resolved that IOB <SINE2<6>> must be placed at site P199.
Resolved that IOB <SINE2<7>> must be placed at site P200.
Resolved that IOB <SINE2<8>> must be placed at site P203.
Resolved that IOB <SINE2<9>> must be placed at site P204.
Resolved that IOB <NCS0_n> must be placed at site P61.
Resolved that IOB <rst> must be placed at site P101.
Resolved that IOB <clk_out1> must be placed at site P184.
Resolved that IOB <clk_out2> must be placed at site P183.
Resolved that IOB <clk_out3> must be placed at site P181.
Resolved that IOB <clk_out4> must be placed at site P180.
Resolved that IOB <clk_out5> must be placed at site P80.
Resolved that IOB <clk_out6> must be placed at site P76.


Device utilization summary:

   Number of External IOBs            97 out of 141    68%
      Number of LOCed External IOBs   42 out of 97     43%

   Number of Slices                 1152 out of 5408   21%
      Number of MULT18X18s             6 out of 16     37%
      Number of RAMB16s                6 out of 16     37%
      Number of SLICEMs               64 out of 1792    3%

   Number of BUFGMUXs                  3 out of 8      37%
   Number of DCMs                      1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98b892) REAL time: 5 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 5 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 5 secs 

Phase 5.8
..................................................
Phase 5.8 (Checksum:c208f2) REAL time: 9 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 9 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 15 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 16 secs 
Total CPU time to Placer completion: 10 secs 


Phase 1: 7016 unrouted;       REAL time: 16 secs 

Phase 2: 6151 unrouted;       REAL time: 18 secs 

Phase 3: 2292 unrouted;       REAL time: 25 secs 

Phase 4: 0 unrouted;       REAL time: 40 secs 

Total REAL time to Router completion: 40 secs 
Total CPU time to Router completion: 26 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         CLKDV_OUT       |  BUFGMUX2| No   |  337 |  0.121     |  0.420      |
+-------------------------+----------+------+------+------------+-------------+
|              CLK0       |  BUFGMUX0| No   |  159 |  0.108     |  0.407      |
+-------------------------+----------+------+------+------------+-------------+
|       NWE_n_BUFGP       |  BUFGMUX1| No   |  257 |  0.130     |  0.429      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS30_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.526     |  1.027      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS20_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.050     |  1.165      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS60_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.656     |  1.156      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS10_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  0.507     |  1.303      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS50_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    9 |  0.726     |  2.188      |
+-------------------------+----------+------+------+------------+-------------+
|my_dds4_DDS40_counterclk |          |      |      |            |             |
|             _outclktemp |   Local  |      |    8 |  1.055     |  1.554      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 236


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.369
   The MAXIMUM PIN DELAY IS:                               5.765
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   4.973

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
        3151        2106        1079         472         208           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 43 secs 
Total CPU time to PAR completion: 27 secs 

Peak Memory Usage:  80 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.