dds1.bld

Verilog编程

Release 6.1.03i - ngdbuild G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd d:\商共享资料\程序\两路正弦波/_ngo -uc
DDS1.ucf -p xc3s400-pq208-4 DDS1.ngc DDS1.ngd 

Reading NGO file "d:/商共享资料/程序/两路正弦波/DDS1.ngc" ...
Reading component libraries for design expansion...
Launcher: "rom1.ngo" is up to date.
Loading design module "d:\商共享资料\程序\两路正弦波\_ngo\rom1.ngo"...
blkmemsp_v5_0, Coregen 6.1i

Annotating constraints to design from file "DDS1.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40928 kilobytes

Writing NGD file "DDS1.ngd" ...

Writing NGDBUILD log file "DDS1.bld"...