armtst.syr

Verilog编程

# Adders/Subtractors               : 1
#      16-bit adder                : 1

Cell Usage :
# BELS                             : 616
#      BUF                         : 1
#      GND                         : 2
#      LUT1                        : 2
#      LUT2                        : 6
#      LUT2_D                      : 1
#      LUT2_L                      : 13
#      LUT3_D                      : 32
#      LUT3_L                      : 256
#      LUT4                        : 32
#      MUXCY                       : 15
#      MUXF5                       : 128
#      MUXF6                       : 64
#      MUXF7                       : 32
#      MUXF8                       : 16
#      VCC                         : 1
#      XORCY                       : 15
# FlipFlops/Latches                : 560
#      FDC                         : 32
#      FDCE                        : 444
#      FDE                         : 16
#      FDPE                        : 68
# RAMS                             : 1
#      RAMB16_S18                  : 1
# Clock Buffers                    : 4
#      BUFG                        : 3
#      BUFGP                       : 1
# IO Buffers                       : 49
#      IBUF                        : 23
#      IBUFG                       : 1
#      OBUF                        : 25
# DCMs                             : 1
#      DCM                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     449  out of   3584    12%  
 Number of Slice Flip Flops:           560  out of   7168     7%  
 Number of 4 input LUTs:               342  out of   7168     4%  
 Number of bonded IOBs:                 49  out of    141    34%  
 Number of BRAMs:                        1  out of     16     6%  
 Number of GCLKs:                        4  out of      8    50%  
 Number of DCMs:                         1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
NWE_n                              | BUFGP                  | 512   |
clkin                              | instance_name_DCM_INST:CLK0| 49    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.567ns (Maximum Frequency: 179.630MHz)
   Minimum input arrival time before clock: 7.384ns
   Maximum output required time after clock: 9.161ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'NWE_n'
Delay:               5.567ns (Levels of Logic = 6)
  Source:            ram_data_0_14 (FF)
  Destination:       ram_data_7_14 (FF)
  Source Clock:      NWE_n rising
  Destination Clock: NWE_n rising

  Data Path: ram_data_0_14 to ram_data_7_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.619   0.465  ram_data_0_14 (ram_data_0_14)
     LUT3_L:I1->LO         1   0.720   0.000  Mmux__COND_1_inst_lut3_2241 (Mmux__COND_1__net434)
     MUXF5:I0->O           1   0.387   0.000  Mmux__COND_1_inst_mux_f5_112 (Mmux__COND_1__net436)
     MUXF6:I0->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f6_56 (Mmux__COND_1__net440)
     MUXF7:I0->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f7_28 (Mmux__COND_1__net448)
     MUXF8:I0->O           2   0.563   0.465  Mmux__COND_1_inst_mux_f8_14 (_n0263<14>)
     LUT3_D:I2->LO         1   0.720   0.000  Mmux__n0032_Result<14>1 (N7467)
     FDCE:D                    0.502          ram_data_10_14
    ----------------------------------------
    Total                      5.567ns (4.637ns logic, 0.930ns route)
                                       (83.3% logic, 16.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkin'
Delay:               4.916ns (Levels of Logic = 17)
  Source:            fre_cont_0 (FF)
  Destination:       sum_15 (FF)
  Source Clock:      clkin rising
  Destination Clock: clkin rising

  Data Path: fre_cont_0 to sum_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.619   0.240  fre_cont_0 (fre_cont_0)
     LUT2_D:I0->LO         1   0.720   0.000  sum_Madd__n0000_inst_lut2_01 (N7725)
     MUXCY:S->O            1   0.629   0.000  sum_Madd__n0000_inst_cy_0 (sum_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_1 (sum_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_2 (sum_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_3 (sum_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_4 (sum_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_5 (sum_Madd__n0000_inst_cy_5)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_6 (sum_Madd__n0000_inst_cy_6)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_7 (sum_Madd__n0000_inst_cy_7)
     MUXCY:CI->O           1   0.091   0.000  sum_Madd__n0000_inst_cy_8 (sum_Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_9 (sum_Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_10 (sum_Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_11 (sum_Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_12 (sum_Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.090   0.000  sum_Madd__n0000_inst_cy_13 (sum_Madd__n0000_inst_cy_13)
     MUXCY:CI->O           0   0.090   0.000  sum_Madd__n0000_inst_cy_14 (sum_Madd__n0000_inst_cy_14)
     XORCY:CI->O           1   0.939   0.000  sum_Madd__n0000_inst_sum_15 (sum__n0000<15>)
     FDC:D                     0.502          sum_15
    ----------------------------------------
    Total                      4.916ns (4.676ns logic, 0.240ns route)
                                       (95.1% logic, 4.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'NWE_n'
Offset:              7.384ns (Levels of Logic = 7)
  Source:            addr<0> (PAD)
  Destination:       ram_data_7_14 (FF)
  Destination Clock: NWE_n rising

  Data Path: addr<0> to ram_data_7_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           288   1.492   1.409  addr_0_IBUF (addr_0_IBUF)
     LUT3_L:I0->LO         1   0.720   0.000  Mmux__COND_1_inst_lut3_1571 (Mmux__COND_1__net302)
     MUXF5:I1->O           1   0.387   0.000  Mmux__COND_1_inst_mux_f5_78 (Mmux__COND_1__net303)
     MUXF6:I0->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f6_39 (Mmux__COND_1__net307)
     MUXF7:I1->O           1   0.563   0.000  Mmux__COND_1_inst_mux_f7_19 (Mmux__COND_1__net308)
     MUXF8:I1->O           2   0.563   0.465  Mmux__COND_1_inst_mux_f8_9 (_n0263<9>)
     LUT3_D:I2->LO         1   0.720   0.000  Mmux__n0032_Result<9>1 (N7457)
     FDCE:D                    0.502          ram_data_10_9
    ----------------------------------------
    Total                      7.384ns (5.510ns logic, 1.874ns route)
                                       (74.6% logic, 25.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkin'
Offset:              5.250ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       fre_cont_15 (FF)
  Destination Clock: clkin rising

  Data Path: rst to fre_cont_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           273   1.492   1.409  rst_IBUF (rst_IBUF)
     LUT1:I0->O           16   0.720   0.995  fre_cont_ClkEn_INV1 (fre_cont_N620)
     FDE:CE                    0.634          fre_cont_0
    ----------------------------------------
    Total                      5.250ns (2.846ns logic, 2.404ns route)
                                       (54.2% logic, 45.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkin'
Offset:              9.161ns (Levels of Logic = 2)
  Source:            sin/B5 (RAM)
  Destination:       dout<7> (PAD)
  Source Clock:      clkin rising

  Data Path: sin/B5 to dout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S18:CLK->DO7    1   3.509   0.240  B5 (dout<7>)
     end scope: 'sin'
     OBUF:I->O                 5.412          dout_7_OBUF (dout<7>)
    ----------------------------------------
    Total                      9.161ns (8.921ns logic, 0.240ns route)
                                       (97.4% logic, 2.6% route)

=========================================================================
CPU : 15.73 / 16.40 s | Elapsed : 16.00 / 17.00 s
 
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Total memory usage is 75908 kilobytes